Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2006-08-15
2006-08-15
Smith, Zandra V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S010000
Reexamination Certificate
active
07091513
ABSTRACT:
In one aspect, the invention encompasses a method of treating the end portions of an array of substantially upright silicon-comprising structures. A substrate having a plurality of substantially upright silicon-comprising structures extending thereover is provided. The substantially upright silicon-comprising structures have base portions, and have end portions above the base portions. A masking layer is formed over the substrate to cover the base portions of the substantially upright silicon-comprising structures while leaving the end portions exposed. The end portions are then exposed to conditions which alter the end portions relative to the base portions. In another aspect, the invention encompasses a method of treating the ends of an array of silicon-comprising emitter structures. A substrate having a plurality of silicon-comprising emitter structures thereover is provided. The emitter structures have base portions and ends above the base portions. A layer of spin-on-glass is formed over the substrate. The layer of spin-on-glass covers the base portions of the emitter structures and leaves the ends exposed. The ends are then exposed to conditions which alter the ends relative to the base portions. In yet another aspect, the invention encompasses a cathode assembly which includes a plurality of silicon-comprising emitter structures projecting over a substrate. The emitter structures have base portions and ends above the base portions, and the ends comprise a different material than the base portions.
REFERENCES:
patent: 3814968 (1974-06-01), Nathanson et al.
patent: 4957881 (1990-09-01), Crotti
patent: 5129850 (1992-07-01), Kane et al.
patent: 5141460 (1992-08-01), Jaskie et al.
patent: 5157002 (1992-10-01), Moon
patent: 5202571 (1993-04-01), Hirabayashi et al.
patent: 5401676 (1995-03-01), Lee
patent: 5421958 (1995-06-01), Fathauer et al.
patent: 5427648 (1995-06-01), Pamulapati et al.
patent: 5430300 (1995-07-01), Yue et al.
patent: 5518950 (1996-05-01), Ibok et al.
patent: 5608285 (1997-03-01), Vickers et al.
patent: 5616519 (1997-04-01), Ping
patent: 5619097 (1997-04-01), Jones
patent: 5627382 (1997-05-01), Canham et al.
patent: 5665657 (1997-09-01), Lee
patent: 5666020 (1997-09-01), Takemura
patent: 5705028 (1998-01-01), Matsumoto
patent: 5729094 (1998-03-01), Geis et al.
patent: 5731214 (1998-03-01), Kurihara
patent: 5817201 (1998-10-01), Greschner et al.
patent: 6130106 (2000-10-01), Zimlich
Boswell, E. et al., “Characterization of Porous Silicon Field Emitter Properties”, J.Vac.Sci. Technol. B 14(3), May/Jun. 1996, pp. 1895-1898.
Sugino, T. et al., “Electron Emission from Boron Nitride Coated Si Field Emitters”, Appl. Phys. Lett. 71(18), Nov. 3, 1997, pp. 2704-2706.
Ko, Y. et al., “Electron Emission and Structure Properties of Cesiated Carbon Films Prepared by Negative Carbon Ion Beam”, J.Appl. Phys. 82(5), Sep. 1, 1997, pp. 2631-2635.
Lee, J. et al., “Emission Characteristics of Silicon Field Emitter Arrays Fabricated by Spin-On-Glass Etch-back Process”, 9thInternatl. Vacuum Microelectronics Conference, St. Petersburg 1996, pp. 380-383.
Takai, M. et al., “Enhanced Electron Emission from n-type Porous Si Field Emitter Arrays”, Appl. Phys. Lett. 66(4), Jan. 23, 1995, pp. 422-423.
Lee, J. et al., “Fabrication and Characterization of Silicon Field Emitter Arrays by Spin-On-Glass Etch-back Process”, J.Vac. Sci. Technol. B 16(1), Jan./Feb. 1998, pp. 238-241.
Matsuura, M. et al., “A Highly Reliable Self-Planarizing Low-k Intermetal Dielectric for Sub-quarter Micron Interconnects”, IEEE 1997, pp. 31.6.1-31.6.4.
ARTICLE: McClatchie, S. et al., “Low Dielectric Constant Flowfill® Technology for IMD Applications”, Electrotech Ltd., Bristol, U.K., undated, 7 pages, date unknown.
ARTICLE: Kiermasz, A. et al., Electrotech Ltd., U.K., “Planarisation for Sub-Micron Devices Utilising a New Chemistry”, presented at DUMIC Conference, California, Feb. 1995, 2 pages.
ARTICLE: Beekmann, K. et al., Electrotech Ltd., U.K., “Sub-Micron Gap Fill and In-Situ Planarisation Using Flowfill™ Technology”, presented at ULSI Conference, Portland, OR, Oct. 1995, pp. 1-7.
Micro)n Technology, Inc.
Rose Kiesha
Smith Zandra V.
Wells St. John P.S.
LandOfFree
Cathode assemblies does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cathode assemblies, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cathode assemblies will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3700693