Castellation wafer level packaging of integrated circuit chips

Details Castellation wafer level packaging of integrated circuit chips Castellation wafer level packaging of integrated circuit chips

2005-09-27

2005-09-27

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S109000, C438S113000, C438S598000

Reexamination Certificate

active

06949407

ABSTRACT:
Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

REFERENCES:
patent: 5356838 (1994-10-01), Kim
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Said F. Al-sarawi and Derek Abbott, 3D VLSI Packaging Technology, The Univ. of Adelaide at, http://www.elecengadelaide.edu.au/Personal/alsarawi/Packaging
ode17.html (Oct. 1997).

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