Electricity: conductors and insulators – Boxes and housings – Hermetic sealed envelope type
Patent
1979-12-27
1982-04-20
Reynolds, B. A.
Electricity: conductors and insulators
Boxes and housings
Hermetic sealed envelope type
357 84, 361424, H05K 506
Patent
active
043260950
ABSTRACT:
A casing for a semiconductor memory chip comprises a barrier intercepting a limited space that envelopes lines of vision between an exposed surface of the chip and an inside end surface of a sealing layer for hermetically sealing a cap and a base member of the casing together and at least towards which alpha particles are emitted from the sealing layer inside surface. The barrier may be made integral with a base member peripheral region having a peripheral surface to be sealed to the cap member by the sealing layer, with that mounting surface of the base member on which the chip is attached, recessed relative to the peripheral surface. The peripheral surface may be either parallel to the mounting surface or canted so that the limited space may be directed inwardly away from the mounting surface. Alternatively, the barrier may comprise a pedestal member having a surface that is an outward extension of the mounting surface, with the mounting surface protruded relative to the peripheral surface. As a further alternative, the barrier may comprise a protrusion on at least one of the peripheral surface and a like surface of the cap member, with the protrusion or protrusions inwardly offset relative to the sealing layer inside surface.
REFERENCES:
patent: 3337678 (1967-08-01), Stelmak
patent: 3544857 (1970-12-01), Byrne et al.
patent: 3697666 (1972-10-01), Wakley et al.
Narumi China Corporation
Reynolds B. A.
Tone D. A.
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