Cascoded NPN electrostatic discharge protection circuit

Details Cascoded NPN electrostatic discharge protection circuit Cascoded NPN electrostatic discharge protection circuit

2001-11-02

2003-06-10

Vu, Bao (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S100000, C257S173000, C257S355000

Reexamination Certificate

active

06577481

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to electronic systems and in particular it relates to electrostatic discharge (ESD) protection.
BACKGROUND OF THE INVENTION
Achieving latch-up-free ESD protection (with minimum trigger voltage) for a pin when the only components available (including NPN transistors) individually snapback below the pin's operation voltage has been a problem in the prior art. Prior art high-voltage ESD circuits rely on stacking lower voltage 2-terminal ESD circuits. For these prior art devices, the trigger voltage of the total circuit is the sum of the individual circuit trigger voltages.
SUMMARY OF THE INVENTION
An electrostatic discharge protection circuit includes: at least two bipolar transistors coupled in series; a top one of the at least two bipolar transistors coupled to a protected node; a bottom one of the at least two bipolar transistors coupled to a common node; at least two resistors coupled in series; each of the at least two resistors is coupled to a corresponding base of one of the at least two bipolar transistors; and a bottom one of the at least two resistors coupled between a base of the bottom one of the at least two bipolar transistors and the common node.


REFERENCES:
patent: 6066971 (2000-05-01), Pappert et al.
patent: 6091594 (2000-07-01), Williamson et al.
patent: 6140682 (2000-10-01), Liu et al.
patent: 6351364 (2002-02-01), Chen et al.
patent: 6353520 (2002-03-01), Andresen et al.
patent: 6430016 (2002-08-01), Marr
patent: 6492686 (2002-12-01), Pappert et al.

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