Cascoded-MOS ESD protection circuits for mixed voltage chips

Details Cascoded-MOS ESD protection circuits for mixed voltage chips Cascoded-MOS ESD protection circuits for mixed voltage chips

1998-08-26

1999-07-27

Medley, Sally C.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 361 91, 327310, H02H 904

Patent

active

059300949

ABSTRACT:
Bias circuits which define control terminal voltages in a cascoded nMOS ESD protection circuit, such that the circuit is in high impedance state (OFF) during normal operation, and low impedance (ON) during an ESD event. G1 and G2 are the driver circuits which define V3 and V4 during an ESD event at the pad. During normal operation, V3 and/or V4 are high and no current flows between the pad and V.sub.SS. During an ESD event, V3 and V4 are high and both devices conduct MOS current as the lateral NPNs turn on. Diode D1 conducts current to charge C.sub.c, the chip capacitance, raising V.sub.DD, enabling G1 and G2 to turn on and raise V3 and V4 to levels greater than the nMOS threshold voltage.

REFERENCES:
patent: 5473500 (1995-12-01), Payne et al.
patent: 5852375 (1998-12-01), Byrne et al.
patent: 5852540 (1998-12-01), Haider
Proceedings of the IEEE, vol. 81, No. 5, May 1993, "ESD: A Pervasive Reliability Convern for IC Technologies," pp. 690-702 (Charvaka Duvvury, Member IEEE and Ajith Amerasekera, Member IEEE).
1995 IEEE, "EOS/ESD Reliability of Deep Sub-Micron NMOS Protection Devices," pp. 284-291 (Sridhar Ramaswamy, Charvaka duvvury and Sung-Mo Kang).

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