Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2002-04-29
2004-09-07
Nguyen, Khanh Van (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S311000
Reexamination Certificate
active
06788143
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to operational amplifiers that include cascode stages. More particular, the present invention is related to a cascode stage that is arranged to operate with reduced input referred offset voltages.
BACKGROUND OF THE INVENTION
A portion of a conventional operational amplifier (
400
) that includes an input stage and a cascode stage is illustrated in FIG.
4
. The cascode stage includes metal oxide semiconductor (MOS) transistors M
401
-M
406
and current sources I
41
-I
42
. The input stage includes MOS transistors M
407
-M
408
and current source I
43
.
Transistor M
401
has a gate that is coupled to a bias potential (VBLkS), a J source that is coupled to node
41
, and a drain that is coupled to node
43
. Transistor M
402
has a gate that is coupled to the bias potential (VBIAS), a source that is coupled to node
42
, and a drain that is coupled to node
44
. Transistor M
403
has a gate and drain that is coupled to node
43
, and a source that is coupled to node
45
. Transistor M
404
has a gate that is coupled to node
43
, a source that is coupled to node
46
, and a drain that is coupled to node
44
. Transistor M
405
has a gate that is coupled to node
46
, a source that is coupled to a high power supply (VHI), and a drain that is coupled to node
45
. Transistor M
406
has a gate and drain that are coupled to node
46
, and a source that is coupled to the high power supply (VHI). Transistor M
407
has a gate that is arranged to receive input signal INM
4
, a source that is coupled to node
47
and a drain that is coupled to node
42
. Transistor M
408
has a gate that is arranged to receive input signal INP
4
, a source that is coupled to node
47
and a drain that is coupled to node
41
. Current sources I
41
-I
43
are coupled to nodes
41
,
42
, respectively.
The input stage is arranged to drive currents into the cascode stage based on the difference in input signals INP
4
and INM
4
. The cascode stage is arranged to receive the drive currents via nodes
41
and
42
, respectively. The input stage and the cascode stage cooperate with one another to provide gain in response to the input signals based on their difference. The output of the cascode stage corresponds to node
44
, which may be used to drive another stage of the amplifier.
SUMMARY OF THE INVENTION
In accordance with the present invention, a cascode stage is arranged to improve performance of an operational amplifier. The cascode stage includes transistors that are arranged to operate as a current mirror. Each side of the current mirror has a corresponding voltage at a corresponding node. One of the corresponding nodes corresponds to a high impedance node that is coupled to a subsequent stage of the amplifier. The voltages at the corresponding nodes are closely matched to one another such that the input referred offset in the amplifier is minimized and the power supply rejection ratio is improved (PSRR). A transistor threshold voltage and a transistor saturation voltage determine the headroom requirements of the cascode stage, such that low power supply voltage operation is possible. The biasing of the transistors in the cascode stage is simplified such that minimal biasing circuitry is required, and overall power consumption may be minimized.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrative embodiments of the invention, and to the appended claims.
REFERENCES:
patent: 4933643 (1990-06-01), Jandu et al.
patent: 5349304 (1994-09-01), Ryat
patent: 5446412 (1995-08-01), Kimyacioglu et al.
patent: 5731739 (1998-03-01), Ho
patent: 5777517 (1998-07-01), Seshita
patent: 5900783 (1999-05-01), Dasgupta
patent: 6150883 (2000-11-01), Ivanov
patent: 6160450 (2000-12-01), Eschauzier et al.
patent: 6194966 (2001-02-01), Dasgupta
Hertzberg Brett A.
Merchant & Gould P.C.
National Semiconductor Corporation
Nguyen Khanh Van
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