Cascode circuits in dual-Vt, BICMOS and DTMOS technologies

Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Reexamination Certificate

active

06211659

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The invention relates generally to cascode circuits, and more particularly to methods and apparatus utilizing cascode-connected transistors in current mirrors, active loads and amplifiers, in conjunction with dual-threshold-voltage (dual-V
T
), BiCMOS and DTMOS technologies.
BACKGROUND OF THE INVENTION
Cascode circuits have been used to buffer or isolate a first transistor from voltage variation by series connecting it with a second transistor. By such buffering, the performance of the first or protected transistor is improved. As used in current mirrors, cascoding tends to reduce the variation of current with applied voltage. Cascoding can also be used in amplifiers to decrease the Miller multiplication of the capacitance between the amplifier output and input.
Conventional current mirrors provide an output current proportional to, and often substantially equal to, an input or reference current. By separating the output current from the reference current on different branches or sides of the current mirror, the output current is available to drive high impedance loads. U.S. Pat. No. 5,311,115, issued May 10, 1994 to Archer, describes a variety of current mirrors and their operation.
While a variety of approaches have been taken, many suffer some drawback, such as low output impedance, high reference side voltage drop, need for depletion devices, temperature sensitivity, troublesome leakage currents, second-order effects, etc.
There remains a need for alternative cascode circuits for use in current mirrors and amplifiers.


REFERENCES:
patent: 4096517 (1978-06-01), Hinn
patent: 4533877 (1985-08-01), Rahim
patent: 4583037 (1986-04-01), Sooch
patent: 4983929 (1991-01-01), Real et al.
patent: 5099205 (1992-03-01), Lewyn
patent: 5142696 (1992-08-01), Kosiec et al.
patent: 5248932 (1993-09-01), Prentice
patent: 5311115 (1994-05-01), Archer
patent: 5341109 (1994-08-01), Ryat
patent: 5359296 (1994-10-01), Brooks et al.
patent: 5361006 (1994-11-01), Cooperman et al.
patent: 5444363 (1995-08-01), Cabler
patent: 5512815 (1996-04-01), Schrader
patent: 5589786 (1996-12-01), Bella et al.
patent: 5680038 (1997-10-01), Fiedler
patent: 5835994 (1998-11-01), Adams
patent: 5933721 (1999-08-01), Hause et al.
patent: 5966005 (1999-10-01), Fujimori
patent: 5982676 (1999-11-01), Poplevine et al.
Chang, M.H., et al., “A Highly Manufacturable 0.25 um Multiple- Vt Dual Gate Oxide CMOS Process for Logic/Embedded IC Foundry Technology”, 1998 Symposium on VLSI Technology Digest of Technical Papers, 150-151, (Jun. 1998).
Chen, Z., et al., “0.18um Dual Vt MOSFET Process and Energy-Delay Measurement”,IEDM96-851, 1996 IEEE, 33.2.1-33.2.4, Apr. (1996).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Cascode circuits in dual-Vt, BICMOS and DTMOS technologies does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Cascode circuits in dual-Vt, BICMOS and DTMOS technologies, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cascode circuits in dual-Vt, BICMOS and DTMOS technologies will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2517939

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.