Cascode amplifying circuit and folded cascode amplifying...

Details Cascode amplifying circuit and folded cascode amplifying... Cascode amplifying circuit and folded cascode amplifying...

2001-11-06

2002-11-05

Nguyen, Patricia (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including plural stages cascaded

C330S253000, C330S261000

Reexamination Certificate

active

06476680

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a cascode amplifying circuit and a folded cascode amplifying circuit.
2. Description of the Related Art
Currently, a cascode amplifying circuit constituted by MOS transistors is widely utilized with an increase in operational frequency of various integrated circuit apparatus since delay of signal by influence of a gate capacitance is comparatively inconsiderable.
According to a basic constitution of a cascode amplifying circuit, as shown by
FIG. 5
, MOS transistors m
1
and m
2
of the same conductive type, for example, N-channel type are connected in cascode, an input signal is applied to the gate of the MOS transistor m
1
on a side of connecting the source to a power source terminal VSS (0V), and an output terminal is provided to the drain of the MOS transistor m
2
the drain of which is connected with a current source and the gate of which is applied with bias voltage. Amplifying gain of such a cascode amplifying circuit is increased by applying negative feedback from the source to the gate of the output transistor of the cascode amplifying circuit. A description will be given thereof as follows.
In
FIG. 5
, the gate terminal of the MOS transistor m
2
is applied with fixed bias voltage Vbias. Now, when transfer conductances of the MOS transistors m
1
and m
2
are respectively designated by notations gm
1
and gm
2
, output resistance values thereof are respectively designated by notations r
01
and r
02
, further, an output resistance value of the cascode amplifying circuit is designated by notation r
0
, the amplifying gain of the cascode amplifying circuit is represented by gm
1
·r
0
. Here, when r
0
is represented by r
01
and r
02
, the following equation is established.
r
0
=r
01
+(
1
+
gm
2
·r
01
)·
r
02
≈gm
2
·r
01
·r
02
  (1)
Therefore, the amplifying gain of the cascode amplifying circuit is represented by the following equation.
gm
1
·r
0
≈gm
1
·gm
2
·r
01
·r
02
  (2)
Now, when negative feedback having gain A is applied from the source to the gate of the MOS transistor m
2
instead of applying the fixed bias voltage Vbias to the gate terminal of the MOS transistor m
2
, the output resistance value r
0
is changed as follows.
 
r
0
=r
01
+(
1
+(
1
+
A
)·
gm
2
·r
01
)·
r
02
≈A·gm
2
·r
01
·r
02
  (3)
Therefore, the amplifying gain of the cascode amplifying circuit becomes as follows.
gm
1
·r
0
≈A·gm
1
·gm
2
·r
01
·r
02
  (4)
It is known that the amplifying gain is increased by a multiplication factor of about A by applying the negative feedback. This can be changed to state as follows. That is, although the change in the output resistance value of the MOS transistor m
2
in accordance with the change in the output value of the cascode amplifying circuit, brings about the change in source voltage of the MOS transistor m
2
, the negative feedback from the source to the gate of the MOS transistor m
2
operates to restrain a change depending on an output value of the output resistance value of the MOS transistor m
2
. As a result, the output resistance of the cascode amplifying circuit looks as high resistance and the amplifying gain is increased.
Meanwhile, an operational range of the output of the circuit of
FIG. 5
is determined by a condition by which the MOS transistor m
1
is brought into a saturated region. That is, when voltage of a drain node x of the MOS transistor m
1
is designated by notation Vx, gate/source voltage of the MOS transistor m
1
is designated by Vgs
1
and threshold voltage thereof is designated by notation Vth
1
, the operational range is prescribed by Vx>Vgs
1
−Vth
1
.
In an actual cascode amplifying circuit, the above-described negative feedback is realized as shown by FIG.
6
and FIG.
7
.
FIG. 6
shows a cascode amplifying circuit increasing amplifying gain by the simplest constitution. According to the constitution, a cascode amplifying circuit comprising the MOS transistors m
1
and m
2
and an active load i
1
, is applied with negative feedback by an amplifying circuit comprising an MOS transistor m
3
and an active load i
2
. Now, when the resistance value of the MOS transistor m
2
is reduced by, for example, a change in output voltage, although voltage of the node x starts increasing, the gate voltage of the MOS transistor m
2
is reduced by operation of the negative feedback and accordingly, the resistance value of the MOS transistor m
2
is restrained from reducing. In this way, the negative feedback by the amplifying circuit comprising the MOS transistor m
3
and the active load i
2
, operates to restrain the change in the resistance value of the MOS transistor m
2
and achieves an effect of increasing the amplifying gain. However, in the circuit of
FIG. 6
, the voltage Vx of the drain x of the MOS transistor m
1
must satisfy at least a voltage relationship of Vx>Vth
3
(notation Vth
3
designates threshold voltage of the MOS transistor m
3
) in order to guarantee operation of the MOS transistor m
3
and there poses a problem that an output operational range becomes narrower than that in the case of the circuit of FIG.
5
. Further, there poses a problem that frequency of pole at the node x is lowered and response of the cascode amplifying circuit is delayed by a mirror effect with respect to gate/drain capacitance of the MOS transistor m
3
. Furthermore, although according to the constitution of
FIG. 6
, the source terminal voltage Vx of the MOS transistor m
2
is determined by the MOS transistor m
3
and the active load i
2
, there also poses a problem that the value of Vx is dispersed by device dispersion of the MOS transistor m
3
or a change in a value of the active load i
2
.
FIG. 7
shows a cascode amplifying circuit improved to increase amplifying gain while avoiding the problems of the circuit of FIG.
6
. According to the constitution, in the cascode amplifying circuit comprising the MOS transistors m
1
and m
2
and the active load i
1
, negative feedback is applied to the transistor m
2
by a folded cascode amplifying circuit constituted by using the MOS transistor m
3
having a conductive type reverse to that of the MOS transistors m
1
and m
2
. Since the MOS transistor m
3
is the MOS transistor having the conductive type reverse to that of the MOS transistor m
1
, there is achieved an advantage that lowering of the drain voltage of the MOS transistor m
1
does not hamper operation of the MOS transistor m
3
and the output voltage range of the cascode amplifying circuit is not narrowed by the negative feedback circuit. Further, since the drain node of the MOS transistor m
3
is connected to the source of an MOS transistor m
12
in cascode, there is achieved an advantage that the mirror effect with respect to the gate/drain capacitance of the MOS transistor m
3
is restrained. Further, the negative feedback portion of
FIG. 7
is provided with a differential input portion constituted by the MOS transistor m
3
and an MOS transistor m
11
and accordingly, there is achieved an advantage that by applying fixed bias voltage to the gate terminal of the MOS transistor m
11
, the source terminal voltage of the MOS transistor m
2
can be adjusted.
However, a large number of transistor elements are needed in the constitution of FIG.
7
and not only the circuit scale is excessively large but also the constitution is constructed by a multiple stage series connection of the transistors and accordingly, there poses a problem that operation at low power source voltage becomes difficult.
SUMMARY OF THE INVENTION
According to an aspect of the invention, there is provided a cascode amplifying circuit comprising a first, a second and a third MOS transistor having a same conductive type, and a fourth MOS transistor having a conductive type reverse thereto, wherein a source of the second MOS transistor is connected to a drain of the first MOS transistor and a drain of the second MOS transistor is connected to an output terminal, the

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