Amplifiers – With semiconductor amplifying device – Including plural stages cascaded
Reexamination Certificate
2000-07-13
2002-03-05
Pascal, Robert (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including plural stages cascaded
C330S291000, C330S292000, C330S100000
Reexamination Certificate
active
06353367
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits and, in particular, to cascode amplifier integrated circuits.
2. Description of the Related Art
Amplifier integrated circuits (ICs) constitute one of the basic types of analog integrated circuits. Amplifier ICs are essentially configured to receive an input voltage signal (V
in
), or input current signal, and, in response, provide a larger output voltage signal (V
out
), or larger output current signal. Such amplifier ICs can be used, for example, as an audio power amplifier or to drive a cathode ray tube (CRT).
FIG. 1
is a simplified schematic simulation diagram of conventional cascode amplifier IC
10
. The conventional cascode amplifier IC
10
is configured to assert an amplified output voltage signal V
out
(at output signal terminal
12
) in response to input voltage signal V
in
(received at input signal terminal
14
), when biased by bias potential V
b
(also referred to as a bias voltage and received at bias input terminal
16
) and provided with power supply voltage V
cc
(received at power supply input terminal
18
).
Conventional cascode amplifier IC
10
includes an input buffer stage circuit
30
that includes bipolar transistor X
8
and resistor R
5
, a gain stage circuit
32
that includes bipolar transistors X
6
and X
7
and resistor R
2
, an output buffer stage circuit
34
that includes interconnected bipolar transistors X
0
, X
1
, X
2
, and X
3
, and a bias stage circuit
36
that includes two diodes D
1
and D
2
. In the conventional cascode amplifier IC
10
of
FIG. 1
, a stray capacitance (represented by dashed stray capacitor
1
) is inherently present at node al
3
of the output buffer stage circuit
34
. Resistors R
1
a
and R
1
b
of conventional cascode amplifier IC
10
constitute a collector load resistor of the gain stage circuit
32
.
One skilled in the art will recognize that
FIG. 1
is representative of a variety of well known conventional cascode amplifier IC configurations. Further descriptions of cascode amplifier ICs are found in U.S. Pat. No. 5,977,610 to Hon Kin Chiu, P. R. Gray and R. G. Meyer,
Analysis and Design of Analog Integrated Circuits, Third Edition,
225-226, 464-466 and 511-513 (John Wiley & Sons, 1993), and U.S. patent application Ser. No. 09/615,293, filed on Jul. 13, 2000, by Peyman Hojabri et al., entitled “Cascode Amplifier Integrated Circuit With Frequency Compensation Capability,” each of which is hereby fully incorporated by reference.
A drawback of conventional cascode amplifier ICs is a slow transient fall response (i.e., a relatively long transient fall response time) due to a relatively slow discharging of the stray capacitance at a node of the output buffer stage (such as at node al
3
of output buffer stage circuit
34
in FIG.
1
). The relatively slow discharging of this node is worsened when the collector load resistance of the gain stage (e.g., resistors R
1
a
and R
1
b
in
FIG. 1
) is large (e.g, 6000 ohms). Still needed in the field, therefore, is a cascode amplifier integrated circuit that provides for a relatively fast transient fall response (i.e., a relatively short transient fall response time) and, therefore, relatively fast operation.
SUMMARY OF THE INVENTION
The present invention provides a cascode amplifier integrated circuit (IC) with a relatively fast transient fall response and, therefore, a relatively fast operation. A cascode amplifier IC according to the present invention includes a bias input terminal configured to receive a bias potential V
b
, (e.g., a 12 volt bias voltage), a power supply input terminal configured to receive a power supply voltage V
cc
(e.g., an 150 volt power supply signal), an input signal terminal configured to receive an input voltage signal V
in
, and an output signal terminal. The cascode amplifier IC also includes a gain stage circuit and an output buffer stage circuit. The output buffer stage circuit includes a plurality of interconnected bipolar transistors. The gain stage circuit is configured to amplify the input voltage signal received at the input signal terminal and to, thereby, produce an amplified voltage signal, while the output buffer stage circuit is configured to receive the amplified voltage signal from the gain stage circuit, increase the current thereof and transmit the resultant amplified voltage signal with increased current to the output signal terminal as an amplified output voltage signal. The cascode amplifier IC further includes a discharge circuit configured to discharge stray capacitance at a node of the output buffer stage circuit. The discharge circuit includes, for example, a bipolar discharge transistor (configured, for example, as an emitter follower device) that reduces the Miller capacitance across the base and collector of one of the interconnected bipolar transistors of the output buffer stage circuit during a transient fall response. The discharging of the stray capacitance by the discharge circuit decreases the transient fall response time of the cascode amplifier IC and, thereby, increases its operation speed.
REFERENCES:
patent: 5416442 (1995-05-01), Hobrecht
patent: 5479133 (1995-12-01), Dow
patent: 5680173 (1997-10-01), White et al.
patent: 5977610 (1999-11-01), Chiu
P.R. Gray and R.G. Meyer,Analysis and Design of Analog Integrated Circuits, Third Edition, 228-226, 464-466 and 511-513 (John Wiley & Sons, 1993).
U.S. application No. 09/615,293, Filed Jul. 13, 2000.
Girard & Equitz LLP
National Semiconductor Corporation
Nguyen Patricia T.
Pascal Robert
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