Cascode amplifier circuitry for amplifying differential signals

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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36518909, 365205, 365206, 365207, 36523005, 365190, H03F 345, G11C 11419

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052988155

ABSTRACT:
Amplifying circuitry for use in a random access memory includes first and second input lines and receives complementary differential signals which respectively represent a binary "1" and a binary "0". The differential signals are respectively applied to first and second transistors connected to provide a rejection of the common mode in the differential signals. Third and fourth transistors also respectively receive the differential signals on the first and second lines. The third and fourth transistors operate as cascode transistors to respectively provide outputs on first and second output lines in accordance with the amplitudes of the signals on the first and second input lines. Fifth and sixth transistors are respectively connected to the third and fourth transistors to limit the currents through the third and fourth transistors.

REFERENCES:
patent: 3967252 (1976-06-01), Donnelly
patent: 4300213 (1981-11-01), Tanimura et al.
patent: 4507759 (1985-03-01), Yasui et al.
patent: 4651302 (1987-03-01), Kimmel et al.
patent: 4725984 (1988-02-01), Ip et al.
patent: 4791607 (1988-12-01), Igarashi et al.
Wyland, "FET Cascode Technique Optimizes Differential Amplifier Performance," Electronics, Jan. 18, 1971, pp. 81-84.

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