Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2011-06-28
2011-06-28
Jackson, Stephen W (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000, C361S091100
Reexamination Certificate
active
07969698
ABSTRACT:
A method and apparatus to provide electrostatic discharge (ESD) protection to electronic circuits using a gate clamp circuit.
REFERENCES:
patent: 5321293 (1994-06-01), Mojaradi et al.
patent: 5336908 (1994-08-01), Roberts
patent: 5463520 (1995-10-01), Nelson
patent: 5610790 (1997-03-01), Staab et al.
patent: 5774318 (1998-06-01), McClure et al.
patent: 5930049 (1999-07-01), Suenaga et al.
patent: 5930094 (1999-07-01), Amerasekera et al.
patent: 6072218 (2000-06-01), Chang et al.
patent: 6078487 (2000-06-01), Partovi et al.
patent: 6091594 (2000-07-01), Williamson et al.
patent: 6147538 (2000-11-01), Andresen et al.
patent: 6249410 (2001-06-01), Ker et al.
patent: 6310379 (2001-10-01), Andresen et al.
patent: 6459553 (2002-10-01), Drapkin et al.
patent: 6724603 (2004-04-01), Miller et al.
patent: 6768616 (2004-07-01), Mergens et al.
patent: 7027276 (2006-04-01), Chen
patent: 7203045 (2007-04-01), Chatty et al.
patent: 7345894 (2008-03-01), Sawtell et al.
patent: 7385793 (2008-06-01), Ansel et al.
patent: 7397642 (2008-07-01), Ker et al.
patent: 7518841 (2009-04-01), Chuang et al.
patent: 7791851 (2010-09-01), Luquette et al.
patent: 2004/0141270 (2004-07-01), Kaneki
patent: 2004/0219760 (2004-11-01), Chaine et al.
patent: 2007/0070659 (2007-03-01), Sawtell
patent: 2007/0097581 (2007-05-01), Khazhinsky et al.
U.S. Appl. No. 11/339,016, Office Action dated Mar. 11, 2008, 14 pages.
Torres, Cynthia A., et al., “Modular, Portable, and Easily Simulated ESD Protection Networks for Advanced CMOS Technologies”, Motorola Inc., 14 pages (2001).
2001 EOS/ESD Symposium, Table of Contents (2001) (citing Torres et al.), 20 pages.
Stockinger, Michael, et al., “Boosted and Distributed Rail Clamp Networks for ESD Protection in Advanced CMOS Technologies”, Motorola Inc., 10 pages (Sep. 2003).
2003 EOS/ESD Symposium Program Schedule, (Sep. 2003) (citing Stockinger et al.), 19 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/339,053 dated Mar. 19, 2008; 5 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/339,053 dated Feb. 11, 2008; 3 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/339,053 dated Feb. 11, 2008; 4 pages.
USPTO Final Rejection for U.S. Appl. No. 11/339,053 dated Oct. 9, 2007; 8 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/339,053 dated Apr. 19, 2007; 13 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/339,016 dated Mar. 13, 2009; 14 pages.
USPTO Advisory Action for U.S. Appl. No. 11/339,016 dated Jan. 12, 2009; 3 pages.
USPTO Final Rejection for U.S. Appl. No. 11/339,018 dated Oct. 7, 2008; 14 pages.
USPTO Non-Final Rejection for U.S. Appl. No. 11/339,016 dated Mar. 11, 2008; 10 pages.
USPTO Final Rejection for U.S. Appl. No. 11/339,016 dated Sep. 2, 2009; 12 pages.
USPTO Advisory Action for U.S. Appl. No. 11/339,016 dated Nov. 12, 2009; 3 pages.
USPTO Notice of Allowance for U.S. Appl. No. 11/339,016 dated Jan. 26, 2010; 8 pages.
Ansel George M.
Nagarajan Muthukumar
Philpott Justin
Cypress Semiconductor Corporation
Jackson Stephen W
Kitov Zeev
LandOfFree
Cascode active shunt gate oxide protect during electrostatic... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Cascode active shunt gate oxide protect during electrostatic..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Cascode active shunt gate oxide protect during electrostatic... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2732558