Cascaded VLSI neural network architecture for on-line learning

Details Cascaded VLSI neural network architecture for on-line learning Cascaded VLSI neural network architecture for on-line learning

1994-09-22

1995-12-26

MacDonald, Allen R.

395 22, 395 24, G06F 1518

Patent

active

054795796

ABSTRACT:
High-speed, analog, fully-parallel and asynchronous building blocks are cascaded for larger sizes and enhanced resolution. A hardware-compatible algorithm permits hardware-in-the-loop learning despite limited weight resolution. A computation-intensive feature classification application has been demonstrated with this flexible hardware and new algorithm at high speed. This result indicates that these building block chips can be embedded as application-specific-coprocessors for solving real-world problems at extremely high data rates.

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