Cascaded driver circuit

Details Cascaded driver circuit Cascaded driver circuit

1990-12-14

1992-11-17

Howell, Janice A.

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Using shift register

377 56, 377 76, 377 80, 377119, 307269, 328 63, 340811, G11C 1900, G09G 300, H03K 2108

Patent

active

051649705

ABSTRACT:
A cascaded driver circuit has two or more stages connected to a common serial data signal line and a common clock pulse signal line. Each stage has a counter circuit for dividing the frequency of the clock pulse signal and an enable latch circuit for latching an enable signal, received from the preceding stage, in response to the divided clock pulses. A data latching circuit in each stage latches serial data in response to the clock pulse signal, starting when the enable signal is latched and stopping when a first number of bits of serial data have been latched. An enable output circuit in each stage sends an enable signal to the next stage when the data latching circuit has latched a second number of bits, the second number being at least two less than the first number.

REFERENCES:
patent: 4285847 (1980-10-01), Masuda et al.
patent: 4393301 (1983-07-01), Svendsen
patent: 4500880 (1985-02-01), Gomersall et al.
patent: 4538145 (1985-08-01), Mitani et al.
patent: 4967192 (1990-10-01), Hirane et al.
patent: 5017914 (1991-05-01), Uchida et al.
patent: 5021775 (1991-06-01), Babin

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