Cascaded DAC architecture with pulse width modulation

Details Cascaded DAC architecture with pulse width modulation Cascaded DAC architecture with pulse width modulation

2011-03-08

2011-03-08

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S144000

Reexamination Certificate

active

07903015

ABSTRACT:
An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at an analog output of the cascaded circuit. Each of the cascade circuits contains a noise-shaping circuit, a PCM (Pulse Code Modulation)-to-PWM (Pulse Width Modulation) converter and a 1-bit P-tap AFIR (Analog Finite Impulse Response) filter DAC. Noise at the output of the cascaded circuit may be further reduced by increasing the number of cascade circuits.

REFERENCES:
patent: 6933872 (2005-08-01), Kranz
patent: 7138395 (2006-11-01), O'Neil et al.
patent: 7308027 (2007-12-01), Gaboriau et al.

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