Cascade current miller circuit

Details Cascade current miller circuit Cascade current miller circuit

2000-04-05

2001-11-13

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

Reexamination Certificate

active

06316989

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a cascade current Miller circuit that is advantageous for obtaining a voltage margin.
BACKGROUND OF THE INVENTION
FIG. 2
shows a conventional cascade current Miller circuit. The cascade current Miller circuit shown in
FIG. 2
has a structure such that p-channel MOS transistors P
10
and P
12
forming a pair of current Miller circuits and p-channel MOS transistors P
11
and P
13
forming a pair of current Miller circuits are connected in cascade with each other. Of these pairs of current Miller circuits, the sources of the pair of current Miller circuits at the upper level (a first pair of current Miller circuits) are connected to a power supply voltage. Drain of the p-channel MOS transistor P
11
, that is the drain of one transistor of the two transistors forming the pair of current Miller circuits at the lower level (a second pair of current Miller circuits), is connected to a constant current source
9
that supply a constant current i.
Further, this cascade current Miller circuit has a structure such that n-channel MOS transistors N
10
and N
12
forming a pair of current Miller circuits and n-channel MOS transistors N
11
and N
13
forming a pair of current Miller circuits are connected in cascade with each other, to form a cascade Miller circuit. Drain of the n-channel MOS transistor N
10
, that is the drain of one transistor of the two transistors forming the pair of current Miller circuits at the upper level (a third pair of current Miller circuits), is connected to the drain of the p-channel MOS transistor P
13
. Thus the drain of the n-channel MOS transistor N
10
is connected to the drain of other transistor of the second pair of current Miller circuits. The sources of the pair of current Miller circuits at the lower level (a fourth pair of current Miller circuits) are connected to the ground. Further, the drain of the n-channel MOS transistor N
12
, that is the drain of other transistor of the third pair of current Miller circuits, is connected to a drain of a p-channel MOS transistor P
15
. The p-channel MOS transistor P
15
and a p-channel MOS transistor P
14
are cascade-connected and their sources are connected to a power supply voltage.
In the above-described structure, a current path (PASS
12
) is formed by the p-channel MOS transistors P
14
and P
15
and the n-channel MOS transistors N
12
and N
13
, and a current path (PASS
10
) is formed by the p-channel MOS transistors P
10
and P
11
. Further, a current path (PASS
11
) is formed by the p-channel MOS transistors P
12
and P
13
and the n-channel MOS transistors N
10
and N
11
. Reference symbols shown at the bottom of the drawing indicate channel lengths (hereinafter to be referred to as L-size) and channel widths (hereinafter to be referred to as W-size) of the respective MOS transistors. Sizes within each bracket indicate L-size and W-size respectively. It is assumed that there is a relationship of PL
12
>PL
13
and NL
11
>NL
10
.
The operation of the cascade current Miller circuit will be explained below. At first, in
FIG. 2
, in the third and fourth current Miller circuits, there is a relationship that the W-size of the n-channel MOS transistor N
12
is n times the W-size of the n-channel MOS transistor N
10
, and the W-size of the n-channel MOS transistor N
13
is n times the W-size of the n-channel MOS transistor N
11
. Accordingly, the current flowing through the current path (PASS
12
) is expressed as i*n by the current Miller transfer of a current i from the current path (PASS
11
).
As shown in the drawing, a potential between the gate and the source (V
GS10
) and a potential between the drain and the source (V
DS10
) are equal, in the n-channel MOS transistor N
10
that is the origin of the current Miller transfer. Similarly, in the n-channel MOS transistor N
11
, a potential between the gate and the source (V
GS11
) and a potential between the drain and the source (V
DS11
) are equal.
Accordingly, a potential between the gate and the source (V
GS13
) has a relationship that V
GS13
=V
GS11
=V
DS11
in the n-channel MOS transistor N
13
that is a current Miller transfer destination. Also, a potential between the gate and the source (V
GS12
) has a relationship that V
GS12
=V
G12
−V
S12
=V
GS11
+V
GS10
−V
DS13
in the n-channel MOS transistor N
12
. V
G12
and V
S12
respectively represent a gate potential and a source potential of the n-channel MOS transistor N
12
.
The following relationship is generally established in the saturation area of a MOS transistor.
V
GS
=SQRT
(&agr;
IL/W
)
+V
TH
where V
GS
, I, L, W and &agr; respectively represent a voltage between the gate and the source, a drain current (I
DS
), L-size and W-size, and a constant.
When &Dgr; is substituted for SQRT (&agr;IL/W), the following
10
relationship is established.
V
GS12
=
 
⁢
Δ
11
+
V
TH11
+
Δ
10
+
V
TH10
-
V
DS13
=
 
⁢
Δ
13
+
V
TH13
+
Δ
12
+
V
TH12
-
V
DS13
&Dgr;
10
, &Dgr;
11
, &Dgr;
12
and &Dgr;
13
respectively represent the above &Dgr; in the n-channel MOS transistors N
10
, N
11
, N
12
and N
13
. V
TH10
, V
TH11
, V
TH12
and V
TH13
respectively represent the above V
TH
in the n-channel MOS transistors N
10
, N
11
, N
12
and N
13
.
In order for the above-described third and fourth pairs of current Miller circuits to operate normally, it is necessary that each MOS transistor always operates in the saturation area. In order for the MOS transistor to operate in the saturation area, it is necessary to satisfy the relationship V
DS
≧V
GS
−V
TH
. Further, as the relationship of V
GS
=V
TH
+&Dgr; is established in the saturation area as described above, in other words it is necessary to satisfy the relationship V
DS
≧&Dgr;.
On the other hand, it is necessary to satisfy the relationship V
DS12
≧V
GS12
−V
TH12
in the n-channel MOS transistor N
12
. This relationship can be modified as follows:
V
D12
-
V
DS13
≥
 
⁢
V
G12
-
V
DS13
-
V
TH12
=
 
⁢
V
G10
-
V
DS13
-
V
TH12
V
D12
≥
 
⁢
V
GS11
+
V
GS10
-
V
TH12
=
 
⁢
V
TH11
+
Δ
11
+
V
TH10
+
Δ
⁢
 
10
-
V
TH12
=
 
⁢
V
TH13
+
Δ
13
+
V
TH12
+
Δ
12
-
V
TH12
=
 
⁢
V
TH13
+
Δ
12
+
Δ
13
In the above expressions, V
DS12
, V
D12
, V
G12
, V
DS13
and V
G10
respectively represent a voltage between the drain and the source of the n-channel MOS transistor N
12
, a drain potential of the same MOS transistor, a gate potential of the same MOS transistor, a voltage between the drain and the source of the n-channel MOS transistor N
13
, and a gate potential of the n-channel MOS transistor N
10
.
In order for the n-channel MOS transistors N
12
and N
13
to be always in saturation areas, it is necessary to satisfy the relationship of V
DS
12
≧&Dgr;
12
and V
DS13
≧&Dgr;
13
, that is, V
D12
(=V
DS12
+V
DS13
)≧&Dgr;
12
+&Dgr;
13
. However, it is necessary to meet the following relationship V
D12
≧V
TH13
+&Dgr;
12
+&Dgr;
13
as described above. Therefore, this cascade current Miller circuit requires an additional voltage of V
TH13
. Thus, there has been known “a cascade current Miller circuit advantageous for obtaining a voltage margin” that has reduced the additionally-used voltage of V
TH13
.
FIG. 3
is a diagram which shows a conventional cascade current Miller circuit advantageous for obtaining a voltage margin. In
FIG. 3
, current paths (PASS
25
), (PASS
20
) and (PASS
21
) and MOS transistors P
20
to P
23
, P
27
, P
28
, N
20
, N
21
, N
28
and N
29
respectively correspond to (PASS
12
), (PASS
10
) and (PASS
11
) and the MOS transistors P
10
to P
13
, P
14
, P
15
, N
10
, N
11
, N
12
and N
13
shown in FIG.
2
.
The cascade current Miller circuit shown in
FIG. 3
includes, in addition to the circuit structure shown in
FIG. 2
, a p-channel MOS transistor P
24
forming a pair of current Miller circuits with the p-channel MOS transist

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