Cascade-connected ROM

Details Cascade-connected ROM Cascade-connected ROM

2005-09-27

2005-09-27

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read only systems

C365S185170, C365S185120

Reexamination Certificate

active

06950325

ABSTRACT:
A serial read-only memory (SROM) device having an address range includes a memory array, an address clock pin for receiving an address clock signal, which starts an address cycle, a data clock pin for receiving a data clock signal, which starts a data cycle, a chip select/cascade (CS/CAS) pin for receiving a first control signal during the address cycle and for receiving a second control signal during the data cycle, a first data pin for receiving an address during the address cycle and for sending data during the data cycle, and a second data pin for receiving external data, the second data pin being connectable to the first data pin through a cascading data path defined therebetween, wherein the external data received at the second data pin may be transmitted to the first data pin when the cascading data path is connected.

REFERENCES:
patent: 4570239 (1986-02-01), Carter et al.
patent: 5740108 (1998-04-01), Okubo

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