Cascade A/D converter

Details Cascade A/D converter Cascade A/D converter

1999-04-30

2001-04-24

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06222477

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a cascade A/D converter with error correction that is error free; and more particulary, to such converter that prevents generation of errors due to noise.
2. Description of the Prior Art
A/D converters include those which are of small scale, low power consumption and low input capacity. This type of converter uses a single clock and provides high speed operation. However, there is a problem of error generation in such converters. The inventors had disclosed in Japan Unexamined Application SN 9/238,077 (1997), a cascade A/D converter which uses a single clock and is operable without errors. Such a device is described in
FIG. 1
, which shows a cascade 5-bit A/D converter that outputs an alternate binary code (also called “gray” code). The device comprises comparators
8
a
-
8
d
; latch circuits
9
a
-
9
e
; D/A converters
10
a
-
10
c
; subtractors
11
a
-
11
c
; comparators
13
a
-
13
h
; logical product circuits (called “AND circuits”)
14
-
17
; exclusive logical sum circuits (called “EOR circuits”)
18
-
20
; logical sum circuits (called “OR circuits”)
21
-
23
; and AND circuits
24
,
25
. Analog input signal
100
a
and digital output signal
101
a
are provided as shown.
Comparators
13
a
,
3
b
and AND circuit
14
comprise window comparator
50
a
. Comparators
13
c
,
13
d
and AND circuit
15
comprise window comparator
50
b
. comparators
13
e
,
13
f
and AND circuit
16
comprise window comparator
50
c
. Comparators
13
g
,
13
h
and AND circuit
17
comprise window comparator
50
d
. OR circuits
21
-
23
and and circuits
24
,
25
comprise error correction circuit
51
.
Analog input signal
100
a
is applied to each non-inverted input terminal of comparators
8
a
and
13
a
, inverted input terminal of comparator
13
b
and the addition input terminal of subtractor
11
a
. The output terminal of comparator
8
a
is connected to latch circuit
9
a
, D/A converter
10
a
, and one input terminal of EOR circuit
18
. The output terminal of D/A converter
10
a
is connected to the subtraction input terminal of subtractor
11
a
. The output terminal of comparators
13
a
and
13
b
are connected to the input terminals of AND circuit
14
. The output terminal of AND circuit
14
is connected to one input terminal of OR circuit
21
and to the negative logic input terminals of AND circuits
15
-
17
,
24
and
25
.
The output terminal of subtractor
11
a
is connected to each noninverted input terminal of comparators
8
b
and
13
c
, inverted input terminal of comparator
13
d
and the addition input terminal of subtractor
11
b
. The output terminal of comparator
8
b
is connected to D/A converter
10
b
, the other input terminal of EOR circuit
18
, and one input terminal of EOR circuit
19
. The output terminal of D/A converter
10
b
is connected to the subtraction input terminal of subtractor
11
b
. Each output terminal of comparators
13
c
and
13
d
is connected to the other two positive logic input terminals of AND circuit
15
, respectively. The output terminal of AND logic circuit
15
is connected to one input terminal of OR circuit
22
and each of the negative logic input terminals of AND circuits
16
,
17
and
25
. The output terminal of EOR circuit
18
is connected to the other input terminal of OR circuit
21
. The output terminal of OR circuit
21
is connected to the latch circuit
9
b.
The output terminal of subtractor
11
b
is connected to each non-inverted input terminal of comparators
8
c
and
13
e
, the inverted input terminal of comparator
13
f
, and the addition input terminal of subtractor
11
c
. The output terminal of comparator
8
c
is connected to D/A converter
10
c
, the other input terminal of EOR circuit
19
, and one input terminal of EOR circuit
20
. The output terminal of EOR circuit
19
is connected to the other input terminal of OR circuit
22
. The output terminal of OR circuit
22
is connected to the positive logic input terminal of AND circuit
24
. The output terminal of AND circuit
24
is connected to latch circuit
9
c
. Each output terminal of comparators
13
e
and
13
f
is connected to the other two positive logic input terminals of AND circuit
16
, respectively. The output terminal of AND circuit
16
is connected to one input terminal of OR circuit
23
and the negative logic input terminal of AND circuit
17
. The output terminal of subtractor
11
c
is connected to the non-inverted input terminals of comparators
8
d
and
13
g
and the inverted input terminal of comparator
13
h.
The output terminal of comparator
8
d
is connected to the other input terminal of EOR circuit
20
. The output terminal of EOR circuit
20
is connected to the other input terminal of OR circuit
23
. The output terminal of OR circuit
23
is connected to the positive logic input terminal of AND circuit
25
. The output terminal of AND circuit
25
is connected to the latch circuit
9
d
. Each output terminal of comparators
13
g
and
13
h
is connected to the other two positive logic input terminals of AND circuit
17
, respectively. The output terminal of AND circuit
17
is connected to latch circuit
9
e
. The output terminal of latch circuit
9
a
-
9
e
are used to output digital output signal
101
a.
The inverted input terminals of comparators
8
a
-
8
d
are grounded. The voltages of +&Dgr;V is applied to the non-inverted input terminals of comparators
13
b
,
13
d
,
13
f
, and
13
h
. The voltages of −&Dgr;V is applied to the inverted input terminals of comparators
13
a
,
13
c
,
13
e
and
13
g
, respectively. However, &Dgr;V=FS/32, wherein FS=full scale.
Operation of the device of
FIG. 1
will now be described with refference to
FIGS. 2 and 3
, which show characteristic curves that indicate each output or each input for analog input signal
10
a
from −FS/2 to +FS/2. In
FIGS. 2 and 3
, lines (a) to (d) show the outputs of comparators
8
a
-
8
d
; lines (e) to (h) show the outputs of window comparators
50
a
to
50
d
; lines (i) to (k) show the outputs of EOR circuits
18
-
20
; and lines (l) to (p) show the inputs to latch circuits
9
a
-
9
e
, respectively.
Comparators
8
a
-
8
d
judge the zero crossing of analog input signal
100
a
, the output of subtractor
11
a
, the output of subtractor
11
b
, and the output of subtactor
11
c
, respectively.
Each of window comparators
50
a
-
50
d
outputs a “high level” signal when the input signal is in each vicinity of “zero” and the output of the window comparator at the preceding stage is at a “low level” signal. Hence, window comparator
50
a
outputs a “high level” signal when analog input signal
100
a
is in each vicinity of “zero” as shown in line (e) of FIG.
2
.
Window comparator
50
b
can output a “high level” signal when analog input signal
100
a
is in each vicinity of “zero” and “+FS/4” as shown in line (b) of FIG.
2
. However, since the output signal from window comparator
50
a
, at the preceding stage is at a “high level” when analog input signal
100
a
is in each vicinity of “zero”, window comparator
50
b
output “high level” signals only in each vicinity of “+FS/4” as shown in line (f) of FIG.
2
.
Window comparator
50
c
can output a “high level” signal in seven positions as shown in line (c) of FIG.
2
. However, since the positions where window comparator
50
a
or
50
b
at the previous states outputs a “high level” signal, are rejected, the output of window comparator
50
c
is of the waveform shown in line (g) of FIG.
2
. Similarly, window comparator
50
d
can output a “high level” signal in 15 positions, as shown iin line (d) of FIG.
2
. However, since the positions where window comparator
50
a
,
50
b
, or
50
c
at the previous stages outputs a “high level” signal are rejected, the output of window comparator
50
d
is of the waveform shown in line (h) of FIG.
2
.
The output signals from EOR circuit
18
-
20
comprise “gray codes” of intermediate bits in digital output signal
101
a
; but, it is know

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