Cascadable parallel to serial converter using tap shift register

Details Cascadable parallel to serial converter using tap shift register Cascadable parallel to serial converter using tap shift register

1990-03-28

1992-12-29

Lee, Thomas C.

Boots, shoes, and leggings

3642387, 3642392, 3649395, 364951, 3649262, 3649265, 364DIG1, 341101, 395500, G06F 500

Patent

active

051758199

ABSTRACT:
A parallel-to-serial FIFO buffer device (100) employs a FIFO buffer (110) for storing words of data; a tap-shift-register portion (112); and a data-shift-register portion (116) for converting from parallel to serial format words of data stored in the FIFO buffer (110), tap-shift-register portion (112) controls the conversion process, receives (150) a serial-input-expansion (RSIX) input signal, and develops (170) a serial-output-expansion (RSOX) output signal. The serial-input-expansion input signal (150) and the serial-output-expansion output signal (170) permit the device (100) to be connected with one, or more, similar, device(s) for word length and/or depth expansion.

REFERENCES:
patent: 4218758 (1980-08-01), Allen et al.
patent: 4298936 (1981-11-01), Shapiro
patent: 4377806 (1983-03-01), Elliot et al.
patent: 4497041 (1985-01-01), Braun
patent: 4750149 (1988-06-01), Miller
patent: 4907186 (1990-03-01), Racey
patent: 5055842 (1991-10-01), Mueller
patent: 5089819 (1992-02-01), Yokosuka et al.

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