Carry Selecting system type adder

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364788, G06F 750

Patent

active

056318600

ABSTRACT:
An adder including a first exclusive OR device, a second exclusive OR device for receiving an output of the first exclusive OR device and a generating signal G(i-1), exclusive ORing the output result of the first exclusive OR device and the generating signal G(i-1), and outputting the calculated result as a sum Si0, and a third exclusive OR device for receiving an output of the second exclusive OR device and a propagating signal P(i-1), exclusive ORing the output result of the second exclusive OR device and the propagating signal P(i-1), and outputting the calculated result as a sum Si1, whereby the amount of hardware and power consumption of the adder used in a carry selecting system is reduced.

REFERENCES:
patent: 4764888 (1988-08-01), Holden et al.
Tan, K. G., Binary Exclusive-OR Carry, IBM Technical Disclosure Bulletin, pp. 747-748 Oct. 1965.
Tyagi, Akhilesh, A Reduced Area Scheme for Carry-Select Adders, IEEE Transactions on Computers, vol. 42, No. 10, pp. 1163-1170 Oct. 1993.

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