Boots – shoes – and leggings
Patent
1997-05-13
1999-02-23
Mai, Tan V.
Boots, shoes, and leggings
36471504, G06F 742, G06F 700
Patent
active
058751238
DESCRIPTION:
BRIEF SUMMARY
FIELD OF INVENTION
This invention relates to ascertaining the leading zero digits of a sum, in particular in Carry-Select-Adders.
PRIOR ART
For a quick addition today mainly parallel working adders consisting of a plurality of individual parallel working digital adding units connected with one another are used. The digits of the same digit significance of the operands to be added are processed simultaneously and thereby as quickly as possible. The time overhead of an addition is shortened under the penalty of the hardware requirements, in particular the space overhead (chip area). Digit in writing a number means the place where a certain figure is positioned. Digits of identical significance are digits written at the same position in front of or behind the decimal point of numbers of the same power.
Parallel adders consist frequently of a plurality of parallel, individual Carry-Select-Adders as known in Prior Art. Each individual adder adds up the digits of the same significance of the operands to be added to make an individual or partial sum. Since it is not yet sure at the time of adding the individual digits owing to the parallel adding, which of said digits must take into account a carry from the prior digit, each individual adder finds the result of the partial sum of one respective digit both with and without the consideration of a carry. Not before the completion of said parallel individual addition it is certain which of the digits will have to take a carry into account, and with the help of the respective carry now the correct result of each individual digit addition, meaning with or without carry, is determined. In other words, each partial adder calculates both a partial sum with a carry and a partial sum without a carry. The correct value of the partial sum within the total addition is subsequently "selected" by means of the found carry--therefrom derives the name of "Carry-Select-Adder".
In floating point processors, two floating point operands are added to one another. For the addition of the floating point numbers, initially the exponents of the two operands are assimilated to one another (alignment), so that subsequently the two operands show the same exponent.
Example
Next the mantissae of the two aligned operands are added to one another: ##EQU1##
In doing so, a not predeterminable number of leading zeroes (zero digits) may appear. The result must be normalised, meaning, the leading zero digits must be counted, the mantissa must be shifted towards the left in accordance with the leading zero digits, and the number of leading zero digits must be subtracted from the exponent.
Shift the mantissa ##EQU2## Correct the exponent
In the adders as known in Prior Art at first the sum of the mantissae of the operands as aligned with one another is calculated. From said sum the number of leading zero digits is determined in a subsequent step and the sum is normalised in conformity with such leading zero digits. Such process of counting leading zero digits is, however, still more critical as to time consumption during the run of a cycle than the result of the mantissa addition, thus slowing down the overall adding process.
FIG. 1 shows an adder 5 in accordance with Prior Art. The two operands A and B are added up to a sum S=A+B in the adder 5, and said sum S is placed by the adder 5 at its output. A counter 10 finds the number of leading zero digits of the sum S and outputs same as a value ZDC (Zero Digit Count). The mantissa of the sum S is shifted to the left in accordance with the number of the leading zero digits ZDC, and the number of the leading zero digits ZDC is subtracted from the exponent of the sum.
SUMMARY OF THE INVENTION
It is an object of the invention to provide an adder which allows a quicker finding of a normalised sum.
It is another object of the invention to provide an adder which allows a quicker finding of the number of the leading zero digits of a sum. Thereby, two floating point figures may quicker be added.
The objects of the invention are solved by devices and metho
REFERENCES:
patent: 4926369 (1990-05-01), Hokenek et al.
patent: 5204825 (1993-04-01), Ng
patent: 5317527 (1994-05-01), Britton et al.
patent: 5424968 (1995-06-01), Okamoto
patent: 5493520 (1996-02-01), Schmookler et al.
patent: 5732007 (1998-03-01), Grushin et al.
Hokenek et al., "Leading-zero anticipator (LZA) in the IBM RISC System/600 floating-point execution unit", IBM J. Res Dev. vol. 34 No. 1, Jan. 1990, pp. 71-77.
Suzuki et al, "A 2.4-ns, 16-bit, 0.5-um CMOS arithmetic logic unit for microprogrammable video signal processor LSIs", May 9, 1993, Proceedings of the custom integrated circuits conference, San Diego, pp. 12.04.01-12.04.04, IEEE.
Dao Trong Son
Gerwig Gunter
Getzlaff Klaus
Haller Wilhelm
Ehrlich Marc A.
International Business Machines - Corporation
Mai Tan V.
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