Carry-select adder structure and method to generate...

Details Carry-select adder structure and method to generate... Carry-select adder structure and method to generate...

2011-03-15

2011-03-15

Malzahn, David H (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07908308

ABSTRACT:
A Carry-Select Adder structure comprising a carry generation network and a multiplexer to select a particular pre-calculatad sum of a bit-group via orthogonal signal levels of a Hot-Carry signal provided by said carry generation network (21), wherein in order to provide orthogonal signal levels of said Hot-Carry signal, the carry generation network (21) comprises two carry lookahead trees (22, 23) working in parallel to each other, wherein a first carry lookahead tree (22) provides a first signal level of the Hot-Carry signal, and a second carry lookahead tree (23) provides a second, compared to the first signal level inverse signal level of the Hot-Carry signal. Furthermore a method to operate such a Carry-Select Adder is described.

REFERENCES:
patent: 7277909 (2007-10-01), Shimooka
patent: 7509368 (2009-03-01), Anders et al.
patent: 7523153 (2009-04-01), Goyal
patent: 2002/0143841 (2002-10-01), Farooqui et al.
patent: 2004/0243658 (2004-12-01), Shimooka
patent: 2006/0253523 (2006-11-01), Anders et al.
patent: 2009/0132631 (2009-05-01), Goyal

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