Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1997-08-05
2004-03-09
Ngo, Chuong Dinh (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
C708S630000, C708S551000
Reexamination Certificate
active
06704761
ABSTRACT:
BACKGROUND OF THE INVENTION
A. Field of the Invention
This application is related to the art of automated processing of numerical data, and more particularly to an improved method for implementing a multiplier/accumulator used in such processing.
B. Background Art
In the art of automated processing of numerical data, as typically carried out in a digital computer, a number of techniques have evolved over the past few decades for reducing the processing time for a given operation, or for accomplishing a given level of processing with lesser hardware complexity, or both. Among such techniques are the use of coding algorithms to effect an encoding of the terms of the multiplier for a given multiplication operation, which encoding results in a material diminution in the number of partial products to be added to find the resultant product of the multiplication, and thus a corresponding savings in the number of adder stages required to find the resultant sum of such partial products. Typical of such coding algorithms is the well-known Booth's algorithm. Artisans in the computer processing arts continue, however, to seek means for further reducing the processing resources required to implement a given computer processing operation.
SUMMARY OF INVENTION
It is accordingly an object of the invention to provide an improved multiplier/accumulator which utilizes less processing resources than such devices which are known in the prior art. To that end, a method is provided for utilizing the processing resources of a multiplier-accumulator combination on a cooperative basis with the result that at least one adder stage in such a combination can be eliminated.
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Farrokh Hashem
Naganathan Subramanian
Raghunath Kalavai J.
Lucent Technologies - Inc.
Ngo Chuong Dinh
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