Carry propagation circuit of parallel-type full adder

Details Carry propagation circuit of parallel-type full adder Carry propagation circuit of parallel-type full adder

1989-06-15

1991-06-18

Malzann, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

050254090

ABSTRACT:
A carry propagation circuit of a parallel-type full adder having a plurality of bits. The carry propagation circuit includes: a control unit for controlling a carry propagation; a main path including a plurality of transfer circuits serially connected and provided for each of the plurality of bits, each transferring a carry signal from a lower bit to a higher bit when it is brought to an ON state by the control unit; and at least one bypath arranged to bypass a predetermined number of the transfer circuits and brought to an enable state or a disable state by the control unit. When the control unit brings the bypath to the enable state, it brings to the OFF state a transfer circuit provided immediately in the lower bit side of the main path seen from a terminated point of the bypath and thus propagates only a carry signal propagated via the bypath to the higher bit side. This contributes to reducing the propagation delay time required for a carry operation to the minimum and thus realizing a high speed operational processing.

REFERENCES:
patent: 4763295 (1988-09-01), Yamada et al.
patent: 4807176 (1989-02-01), Yamada et al.

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