Boots – shoes – and leggings
Patent
1993-10-19
1996-04-16
Mai, Tan V.
Boots, shoes, and leggings
G06F 750
Patent
active
055089526
ABSTRACT:
A carry-lookahead/carry-select binary adder includes a plurality of Manchester carry-lookahead cells arranged by length in monotonically increasing order at a first level and a carry-lookahead cell(s) at a second level connected to the first level cells. The cells generate corresponding groups of carry-propagate and carry-generate bits for respective portions of a first and a second binary operand to be summed. From each of the groups, a carry signal is derived for selecting the outputs of one of two parallel binary ripple adders. Based on the selection, the correct sum bits for respective portions of the first and a second binary operands are output. By arranging the first level cells in monotonically increasing order, the summation can occur quickly and each of the portions can be summed in a relatively uniform amount of time. In particular, the critical path delays associated with the summation of each of the portions are kept relatively uniform, based on a sum of the square of the length delay approximation. In the preferred embodiment, each of the binary ripple adders are replaced by a smaller-scale version of the hybrid adder itself. The hybrid adder can also be configured to add two 56-bit operands, which is ample for performing summation of the 52-bit mantissas of IEEE Standard-754 double-precision floating-point numbers. At this level of integration, a plurality of groups of Manchester carry-lookahead cells are implemented at the first level, and each group is arranged in monotonically increasing order.
REFERENCES:
patent: 3700875 (1972-10-01), Saenger et al.
patent: 3805045 (1974-04-01), Larsen
patent: 4525797 (1985-06-01), Holden
patent: 4737926 (1988-04-01), Vo et al.
patent: 4761760 (1988-08-01), Tomoji
patent: 4764888 (1988-08-01), Holden et al.
patent: 4901269 (1990-02-01), Stoelzle
patent: 4905180 (1990-02-01), Kumar
patent: 5027312 (1991-06-01), Knauer et al.
patent: 5047976 (1991-09-01), Goto et al.
patent: 5117386 (1992-05-01), Persoon et al.
patent: 5122982 (1992-06-01), Cohn
patent: 5136539 (1992-08-01), Kumar
patent: 5327369 (1994-07-01), Ashkenazi
Waser, "High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing", 1978 IEEE, pp. 19-29.
Joseph J. F. Cavanagh, Digital Computer Arithemtic Design and Implementation, McGraw-Hill, Inc., 1984, pp. 98-124.
Alain Guyot, et al., A Way to Build Efficient Carry-Skip Adders, IEEE Transactions on Computers, vol. C-36, No. 10, Oct. 1987, pp. 1144-1152.
Inseok S. Hwang and Aaron L. Fisher, Ultrafast Compact 32-bit CMOS Adders in Multiple-Output Domino Logic, IEEE Journal of Solid-State Circuits, vol. 24, No. 2, Apr. 1989, pp. 358-369.
Pak K. Chan and Martine D. F. Schlag, Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip, IEEE Transactions on Computers, vol. 39, No. 8, Aug. 1990, pp. 983-992.
Tom Lynch and Earl Swartzlander, The Redundant Cell Adder, IEEE, 1991, pp. 165-170.
H. R. Srinivas and Keshab K. Parhi, A Fast VLSI Adder Architecture, IEEE Journal of Solid-State Circuits, vol. 27, No. 5, May 1992, pp. 761-767.
Thomas Lynch and Earl E. Swartzlander, Jr., A Spanning Tree Carry Lookahead Adder, IEEE Transactions on Computers, vol. 41, No. 8, Aug. 1992, pp. 931-939.
Pak K. Chan, et al., Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming, IEEE Transactions on Computers, vol. 41, No. 8, Aug. 1992, pp. 920-930.
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