Carry look-ahead technique having a reduced number of logic leve

Details Carry look-ahead technique having a reduced number of logic leve Carry look-ahead technique having a reduced number of logic leve

1988-02-16

1989-08-15

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 750

Patent

active

048581682

ABSTRACT:
A 32-bit adder utilizes an optimal partitioning scheme for improving the 32-bit carry look-ahead. Instead of relying on the powers-of-four partitioning scheme used in prior art adders, the inventive technique uses "double generate" and "double propagate" terms. These represent the generate and propagate functions for two bits. In addition, "double group geneate" and "double group propagate" terms are produced, which represent the generate and propagate terms for a 8-bit groups. In this manner, a partition of 1-bit/8-bit is obtained, rather than the prior art 1-bit/4-bit/16-bit. The critical path is typically shortened from 7 logic levels to 5 logic levels, resulting in faster operation. The double functions are advantageously implemented using logic circuitry having two (or more) outputs per gate.

REFERENCES:
patent: 3993891 (1976-11-01), Beck et al.
patent: 4584661 (1986-04-01), Grundland
patent: 4623981 (1986-11-01), Wolrich et al.
patent: 4764886 (1988-08-01), Yano
ISSCC'88, Session XI: "High-Speed Logic"; Tham 11.2: A 3.1ns 32b CMOS Adder in Multiple Output Domino Logic, Hwang et al., pp. 140-141, 332-333.
"High-Speed Compact Circuits with CMOS", IEEE Journal of Solid-State Circuits, vol. SC-17, No. 3, June 1982, pp. 614-619, Krambeck et al.
"Digital Computer Arithmetic Design and Implementation," Cavanagh, University of Santa Clara, McGraw-Hill, 1984, pp. 107-117.

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