Carry look-ahead circuit and adder using same

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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07395307

ABSTRACT:
A carry look-ahead circuit for an adder to decrease circuit size and power consumption. The carry look-ahead circuit is composed of 2-input NAND gates101, 102, 2-input NOR gate103, AND-NOR type composite gates201, 202, OR-NAND type composite gate251, or other gates with 2 or less series stages of transistors inserted between the output terminal and the power source line or the ground line. When the number of series stages of transistors increases, the driving power decreases. Consequently, in order to maintain the same operation speed, it is necessary to increase the transistor size. The use of multi-input NAND gates and NOR gates, makes it possible to suppress the number of series stages of transistors and to reduce the transistor size. As a result, it is possible to decrease the circuit size and power consumption.

REFERENCES:
patent: 4559608 (1985-12-01), Young et al.
patent: 5122982 (1992-06-01), Cohn
patent: 5278783 (1994-01-01), Edmondson
patent: 5877973 (1999-03-01), Kato et al.
patent: 6199090 (2001-03-01), Mansingh et al.

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