Boots – shoes – and leggings
Patent
1995-10-20
1998-09-01
Ngo, Chuong Dinh
Boots, shoes, and leggings
36472503, G06F 750, G06F 1714
Patent
active
058019790
ABSTRACT:
An inverse discrete cosine transform processor for transforming a video signal from frequency domain signals into spatial domain signals. A bus converter receives DCT coefficient data from parallel processing paths and converts the DCT coefficient data to even and odd processing paths. Partial IDCT processors convert, in parallel, the coefficient data from the even and odd processing paths to produce intermediate coefficient values by performing a one dimensional transform. The intermediate coefficient values are transposed in a transpose RAM to produce transposed intermediate coefficient values which are subsequently separated into even and odd processing paths and converted in parallel to produce pixel values by performing a one dimensional transform. The 1-D IDCT processors each include input section circuits which each receive four-bits of 12-bit or 16-bit input values and provides one bit of each of four input values in a four clock cycle time period. Each of the 1-D IDCT processors also includes an accumulator section which includes adders which sum M-1 bit values to produce an M-bit output value. Any bits of less significance than the M-1 input values are applied to carry logic circuitry which generates a carry signal without generating a sum signal for these less significant bits. The carry is combined with output value produced by each accumulator section.
REFERENCES:
patent: 4760543 (1988-07-01), Ligtenberg et al.
patent: 4791598 (1988-12-01), Liou et al.
patent: 5126962 (1992-06-01), Chiang
patent: 5197021 (1993-03-01), Cucchi et al.
patent: 5299029 (1994-03-01), Shirasawa
patent: 5357453 (1994-10-01), Kim et al.
patent: 5361220 (1994-11-01), Asano
patent: 5387982 (1995-02-01), Kitaura et al.
patent: 5434808 (1995-07-01), Cohen
patent: 5473559 (1995-12-01), Makino
patent: 5481487 (1996-01-01), Jang et al.
patent: 5583803 (1996-12-01), Matsumota et al.
patent: 5590067 (1996-12-01), Jones et al.
patent: 5596518 (1997-01-01), Toyokura et al.
patent: 5598361 (1997-01-01), Nagamatsu et al.
patent: 5610849 (1997-03-01), Huang
Stanley, A. White, "Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review", IEEE ASSP Magazine, pp. 4-19, Jul. 1989.
Kwok K. Chau, I-Fay Wang, and Creighton L. Eldridge, "VLSI Implementation Of A 2-D DCT In A Compiler", VLSI Design Laboratory, Texas Instruments, V4.6, pp. 1233-1236, IEEE 1991.
IEEE Circuits and Systems Standards Committee, "IEEE Standard Specifications for the Implementations of 8.times.8 Inverse Discrete Cosine Transform", IEEE Std. 1180-1990, pp. 1-13, Mar. 18, 1991.
M. Maruyama, H. Uwabu, I, Iwasaki, H. Fujiwara, T. Sakaguchi, M.T. Sun, and M.L. Liou, "VLSI Architecture and Implementation of a Multi-Function, Forward/Inverse Discrete Cosine Transform Processor", SPIE vol. 1360 Visual Communications and Image Processing '90, pp. 410-417.
ISO/TEC 13818-22: 1995 E, "Information Technology--Generic Coding of Moving Pictures and Associated Audio Information: Video", Recommendation ITU-T H.262, pp. 1-231.
Matsushita Electric Corporation of America
Ngo Chuong Dinh
LandOfFree
Carry logic that produces a carry value from NLSBs for a ROM acc does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Carry logic that produces a carry value from NLSBs for a ROM acc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Carry logic that produces a carry value from NLSBs for a ROM acc will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-276946