Carry increment adder using clock phase

Details Carry increment adder using clock phase Carry increment adder using clock phase

1996-06-26

1999-06-15

Malzahn, David H.

Boots, shoes, and leggings

36478703, G06F 750

Patent

active

059128330

ABSTRACT:
A carry increment adder (CIA) using a clock phase in which the CIA performs at an increased speed but uses a much smaller chip area than a general fast adder structure. In the CIA from 1 to N partial adder modules (RCA) which generate partial sum and partial carry value using desired bits of two input data (a, b) as a module. The wider the addition bits width, the greater the speed and the smaller the chip area used.

REFERENCES:
patent: 4683548 (1987-07-01), Mlynek
patent: 4761760 (1988-08-01), Tomoji
patent: 4942549 (1990-07-01), Jutand et al.
patent: 5097436 (1992-03-01), Zurawski
patent: 5144575 (1992-09-01), Jeong et al.
patent: 5257218 (1993-10-01), Poon
patent: 5394352 (1995-02-01), Nakano

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