Carry-forming unit

Details Carry-forming unit Carry-forming unit

1982-02-04

1984-09-11

Smith, Jerry

Boots, shoes, and leggings

G06F 750

Patent

active

044714556

ABSTRACT:
The carry-forming unit comprises a first MOSFET, a second MOSFET, a third MOSFET, a first inverter, a second inverter, an OR-NOT circuit. The input of the first inverter is connected to the input of the first preparatory function. The output of the first inverter and the drain of the first MOSFET are connected to a carry output. The gate of the first MOSFET and the input of the second inverter are connected to the input of second preparatory function. The sources of the first and second MOSFET's and a first input of the NOR-circuit are connected to the carry input of the carry-forming unit. The drain of the second MOSFET is connected to a power supply line while the pulse input of the first inverter and the gate of the second MOSFET are connected to a clock signal line. The source of the third MOSFET is connected to a common bus and its drain--to the source of the first MOSFET. A second input of the OR-NOT circuit is connected to the output of the second inverter and the output--to the gate of the third MOSFET. The present invention helps increase the speed of multi-bit adders, priority and comparator circuits, which results in an increased capacity of computer systems.

REFERENCES:
patent: 3249747 (1966-05-01), Booher
patent: 3728532 (1973-04-01), Pryor
patent: 3878986 (1975-04-01), Hirasawa
patent: 3932734 (1976-01-01), Parsons
patent: 4016546 (1977-04-01), Bennett et al.
patent: 4071905 (1978-01-01), Oguchi et al.
patent: 4152775 (1979-05-01), Schwartz
patent: 4179746 (1979-12-01), Tubbs
patent: 4228520 (1980-10-01), Letteney et al.
patent: 4323982 (1982-04-01), Eichrodt et al.
patent: 4369500 (1983-01-01), Fette
Weller, C. W., "A High-Speed Carry Circuit for Binary Adders", IEEE Transactions on Computers, vol. C-18, No. 8, Aug. 1969, pp. 728-732.

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