Carrier wafer having alignment keys and supporting a chip

Details Carrier wafer having alignment keys and supporting a chip Carrier wafer having alignment keys and supporting a chip

2011-08-23

2011-08-23

Nguyen, Khiem D (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257SE23179

Reexamination Certificate

active

08004097

ABSTRACT:
Methods for manufacturing an integrated wafer scale package that reduces a potential misalignment between a chip and a pocket of a carrier substrate. According to one aspect of the present invention, a method for manufacturing a semiconductor device includes a photoresist layer disposed on a carrier substrate, a chip placed onto a surface of the photoresist layer. The photoresist layer is patterned using the chip as a mask. The chip is removed from the photoresist layer after the patterning step. A pocket is formed in the carrier substrate, and the chip that was removed is placed into the pocket formed in the carrier substrate.

REFERENCES:
patent: 5704116 (1998-01-01), Gamota et al.
patent: 6057206 (2000-05-01), Nguyen et al.
patent: 6140707 (2000-10-01), Plepys et al.
patent: 2002/0014703 (2002-02-01), Capote et al.

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