Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-03-15
2002-12-10
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C134S001200, C204S192320, C216S067000, C438S725000
Reexamination Certificate
active
06492272
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application contains subject matter similar to subject matter disclosed in copending U.S. patent application Ser. No. 09/805,974, filed on Mar. 15, 2002.
1. Field of the Invention
The present invention relates to improved methods for performing plasma ashing of a photoresist material. More specifically, the present invention relates to improved methods for performing plasma ashing of patterned photoresist layers subsequent to formation of openings in a dielectric layer as part of multi- metallization level processing utilized in the fabrication of high integration density, semiconductor integrated circuit (IC) devices having submicron-dimensioned design features, wherein deleterious reaction of underlying metallization features with the gas(es) utilized for plasma ashing of photoresist is advantageously eliminated, or at least substantially reduced.
2. Background of the Invention
The escalating requirements for high integration density and performance associated with ultra large-scale (“ULSI”) integration semiconductor device wiring and interconnection require responsive changes in interconnection technology. Such escalating requirements have been difficult to satisfy in terms of providing a low resistance-capacitance (“RC”) interconnection pattern, particularly wherein the various metallization features, e.g., vias, contacts, trenches, etc., are submicron-dimensioned and have high aspect ratios due to micro-miniaturization.
Conventional semiconductor IC devices typically comprise a semiconductor substrate, such as a monocrystalline silicon (Si) wafer including a plurality of active device regions formed thereon or therein, and a plurality of pairs of overlying, sequentially formed inter-layer dielectrics (“ILD”s) and patterned metal layers. An integrated circuit is formed therefrom containing a plurality of electrically conductive patterns comprising conductive lines separated by interwiring spaces, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of different layers, i.e., upper and lower vertically spaced-apart layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes an electrical contact with an active device region on or in the semiconductor substrate, such as a source or drain region of a transistor. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor IC devices comprising five (5) or more such levels of vertically interconnected metallization are becoming more prevalent as device geometries decrease into the deep submicron range.
A conductive plug filling a via opening is typically formed by a process sequence comprising: (1) depositing an inter-layer dielectric (ILD) on a patterned, electrically conductive layer, e.g., a metal layer comprising at least one metal feature; (2) forming a desired opening in the ILD, as by conventional photolithographic masking and etching techniques, and filling the opening with an electrically conductive material, e.g., tungsten (W); and (3) removing excess conductive material deposited on the surface of the ILD during filling of the opening, as by chemical-mechanical polishing/planarization (“CMP”).
One such method for fabricating electrically conductive vias is termed “damascene” type processing and basically involves the formation of an opening in an ILD which is filled with a metal plug. “Dual-damascene” processing techniques involve formation of an opening in an ILD comprising a lower, contact or via opening section communicating with an upper, trench opening section, followed by filling of both the lower and upper sections of the opening with an electrically conductive material, typically a metal or metallic material, to simultaneously form a conductive (via) plug in electrical contact with a conductive line.
Referring now to FIGS.
1
(A)-
1
(C), illustrated therein in schematic, cross-sectional form, are several stages of a typical photolithographic masking+ etching process conventionally utilized for forming an opening in an ILD layer for use as, for example, a via, bus line, bit line, word line, or interconnection line in metallization processing of semiconductor IC devices, e.g., according to the above-described damascene-type techniques.
Referring particularly to
FIG. 1
, precursor structure
1
is of conventional structure and includes a lower metal feature
11
, e.g., of copper (Cu) or a Cu-based alloy, in-laid within a first, or lower, ILD layer
10
overlying a substrate (not shown in the figure for illustrative simplicity), typically a monocrystalline Si wafer. Precursor structure
1
further comprises a thin nitride layer
14
, typically a silicon nitride (Si
x
N
y
) layer from about 300-1000 Å thick, e.g., about 500 Å thick, formed, as by conventional techniques, to overlie the ILD layer
10
and its in-laid metal feature
11
. Second, or upper ILD layer
12
is formed, as by conventional deposition techniques, to overlie the thin nitride layer
14
. In this context, portion
14
′ of thin nitride layer
14
overlying metal feature
11
serves both as an etch stop layer during patterning of the second, upper ILD layer
12
to form a desired opening
15
therein as part of the metallization process, and as a protective layer for preventing deleterious reaction of the metal feature
11
, e.g., oxidation, nitridation, etc., during processing antecedent to filling the opening with a metal material, e.g., during reactive plasma etching of the second, upper ILD layer
12
to form opening
15
. Organic-based photoresist layer
13
formed over the second, upper ILD layer
12
and patterned by conventional photolithographic masking and etching techniques serves as an etch mask during the reactive plasma etching.
Adverting to FIG.
1
(B), subsequent to formation of opening
15
in second, upper ILD layer
12
, according to conventional processing methodology, the patterned photoresist mask is then removed by means of a plasma ashing process, typically utilizing an oxygen (O
2
) or nitrogen (N
2
)-based plasma (or a mixed O
2
/N
2
or N
2
/H
2
plasma) with admixed argon (Ar) gas functioning as an inert carrier gas/diluent for the O
2
, N
2
, O
2
/N
2
, or N
2
/H
2
.
As utilized herein, the term “plasma ashing” designates plasma processes for removing organic-based photoresists, e.g., subsequent to their use as etch masks, etc. By way of illustration only, a typical O
2
-based plasma ashing reaction is conducted (in a suitable reactor) between a carbon (C)- and hydrogen (H)-containing photoresist material generally designated by the formula C
x
H
y
, and plasma-activated oxygen species, generally designated as O
*
. according to the following equation, in which each of the reaction products is volatile and thus readily removed from the reactor chamber:
C
x
H
y
+O
*
=CO(gas)+H
2
O(gas)+CO
2
(gas)
The plasma ashing process is conducted within the interior space of a suitably configured reactor with radio frequency (RF) or microwave (&mgr;wave) energization at an applied power density determined in view of a number of process/apparatus parameters, including, inter alia, the reactor size, particular ashing gas or gases, their flow rate(s) and pressure(s), photoresist composition, desired ashing rate, substrate temperature, etc. As a consequence of the plurality of process variables/parameters, the power level applied to the reactor typically is optimized for use in a particular situation/application.
As indicated above, the active plasma ashing gases, e.g., O
2
, N
2
, O
2
/N
2
, or N
2
/H
2
mixtures, are frequently supplied to the interior space of the plasma reactor admixed with inert argon (Ar) gas as a carrier gas/diluent, in order to facilitate plasma formation and moderate the plasma ashing reaction. However, as indicated in FIG.
1
(B), argon ions (Ar
+
) generated
Okada Lynne A.
Wang Fei
Advanced Micro Devices , Inc.
Powell William A.
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