Carrier element for a semiconductor chip

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Smart card package

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S739000, C257S692000, C257S668000, C257S774000, C257S778000, C257S698000, C438S118000, C438S119000

Reexamination Certificate

active

06326683

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a carrier element for a semiconductor chip, in particular for incorporation in smart cards. The carrier element has a metallic sheet laminated onto a non-conductive sheet and is structured so that two parallel rows of contact areas are formed which run along opposite main edges of the carrier elements. The semiconductor chip is disposed on that side of the non-conductive sheet that is opposite to the metallic sheet, and is electrically connected to contact areas through cutouts in the non-conductive sheet.
Such carrier elements are disclosed, for example, in German Patent DE 34 24 241 C2 and are employed to a great extent in smart cards. To produce them, a non-conductive sheet, which is nowadays preferably composed of glass-fiber-reinforced epoxy resin, is laminated with a conductive sheet preferably composed of surface-refined copper. Structures are etched into the conductive sheet, which structures form mutually insulated contact areas which are disposed in two mutually parallel rows on the long sides of a central area. It is usual for one of the outer contact areas to be formed in one piece with the central contact area. Before the lamination operation, holes are stamped into the non-conductive sheet. The holes enable access to the contact areas in order to be able to connect a semiconductor chip electrically to the contact areas, with the result that contact can be made with the the semiconductor chip by a reading device via the contact areas. It is also possible to provide a central stamping for the accommodation of the semiconductor chip, as is the case describe in German Patent DE 34 24 214 C2, for example, in order to reduce the total height of the carrier element-chip configuration.
Carrier elements of the above-described type are known from French Patent Nos. FR-A-2617668 and FR-A-2684236. With the carrier elements described there, the contact areas are connected with conductor tracks that lead to a joint terminal, in order to perform in a simple manner a galvanic surface processing (refinement).
Nowadays, the known carrier elements usually have an approximately rectangular base area with the two rows of contact areas running along two opposite edges of the carrier element.
In the past, semiconductor chips for smart cards fulfilled almost exclusively specific storage functions and, on account of their serial data input, were suitable only for use in smart cards. However, with the increasing dissemination of smart cards having microprocessor functions, the semiconductor chips used therefor have become more generally usable, since microprocessors having a serial input, in particular those with special coprocessors, are used even when they are not packaged in a smart card. For example, they can also be incorporated in PCMCIA cards or generally be employed on circuit boards.
The technology that is preferred nowadays for connecting a semiconductor chip and a circuit board is soldering in accordance with SMD technology (Surface Mounted Device). In this case, a solder paste is applied to the circuit board by screen printing and the semiconductor chips, which are housed as SMDs, are then positioned on this. The circuit board is subsequently transferred to a furnace in order to melt the solder and thereby establish a connection between the circuit board and the semiconductor chip.
Chip housings with an SMD capability have specially shaped terminals that permit automatic mounting and a likewise automatic soldering operation. The soldered connection must be reliable and be produced at defined points without the solder flowing away and, as a result, short circuits arising or good contact not being produced.
In contrast to this, today's carrier elements for smart cards have relatively large-area contacts, which primarily serve to establish reliable contact with scanning tips of a reading device. The ISO standard ISO 7816, in particular, stipulates the necessary minimum size and position of the contact areas.
It is therefore necessary to provide different housings or chip carriers for different applications, which leads to an increase in the production costs on account of different manufacturing processes, logistics, materials, etc.
Swiss Patent CH 654 143 A5 discloses providing a carrier element for smart cards for other mounting methods as well, for example for incorporation in hybrid circuits. However, in the carrier element of that document, the contact areas for the smart card mounting and terminals which are formed in one piece with the contact areas lie in different planes, thereby necessitating complicated production. Moreover, the terminals are provided for making direct contact with the semiconductor chip, with the result that they cannot also be used as soldering lugs since this would damage the chip.
European Patent Application EP 0 311 435 A2 also describes a carrier element for smart cards which is made of a metal-laminated non-conductive substrate in which the metal lamination is structured into contact areas. In this case, conductor tracks forming terminals are formed in one piece with the contact areas. However, the terminals serve for making direct contact with a semiconductor chip disposed in a cutout in the substrate and, for this purpose, project into the region of the cutout. The terminals cannot, therefore, be used as soldering lugs in this case either.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a carrier element for a semiconductor chip which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which both complies with the ISO standards applicable to smart cards and also has SMD mounting capability.
With the foregoing and other objects in view there is provided, in accordance with the invention, in combination with a semiconductor chip, a carrier element for mounting the semiconductor chip, including: a non-conductive sheet having opposite main edges, a first side and a second side opposite the first side, the non-conductive sheet having a plurality of holes formed therein; a metallic sheet laminated onto the first side of the non-conductive sheet and has two parallel rows of contact areas running along the opposite main edges of the non-conductive sheet, the metallic sheet has conductor tracks with given widths and terminals running in one plane with the metallic sheet, the terminals have dimensions and spacings between one another corresponding to ISO-standards for surface mounting device soldering, each of the contact areas is integrated in one-piece with a respective conductor track and the contact areas have widths greater than the given widths of the conductor tracks; and the semiconductor chip is disposed on the second side of the non-conductive sheet opposite the metallic sheet, the semiconductor chip is electrically connected to the contact areas through the plurality of holes in the non-conductive sheet.
During the production of a copper-laminated glass epoxide carrier element, in the manner according to the invention, not only contact areas but also narrow conductor tracks connected in one piece thereto are etched. The copper sheet should in this case have a thickness of at least 35 &mgr;m, preferably about 70 &mgr;m, in order to ensure a sufficiently large spacing between the circuit board and the non-conductive plastic sheet, thereby reducing the risk of an electrical short circuit due to the solder paste. The non-conductive sheet is preferably made of Kapton, which has sufficient temperature stability for SMD soldering. The narrow conductor tracks, which preferably have a width of about 0.4 mm and thus comply with the SMD standard, enable clearly defined soldering. The conductor tracks advantageously run parallel to one another and at the same time preferably have a spacing between their center lines of about 1.27 mm, which likewise complies with the SMD standard. In this case, the conductor tracks can run both parallel to the rows of the contact areas and perpendicular thereto. In princi

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Carrier element for a semiconductor chip does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Carrier element for a semiconductor chip, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Carrier element for a semiconductor chip will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2582580

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.