Carrier detect circuit

Communications: electrical – Digital comparator systems

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Details

307235N, 340147PC, 340172, H04Q 916

Patent

active

039900487

ABSTRACT:
A detector circuit utilizing two comparators, the first of which initially switches output at a first bias level, and the second of which switches output responsive to a preselected voltage on a capacitor. The voltage on the capacitor is controlled by the output of the first comparator which charges and discharges it through a dual time constant arrangement in order to sensitize the detector to activate a recorder after a preselected delay only upon receipt of a particularly shaped long duty cycle input signal. After receipt of the input signal, the bias level of the first comparator is changed so as to prevent switching until receipt of a second preselected input signal. In addition, after receipt of the first input signal, the time constant of charge-discharge arrangement for the capacitor is again altered.

REFERENCES:
patent: 3573638 (1971-04-01), Cox, Jr.
patent: 3651470 (1972-03-01), Healey et al.
patent: 3715579 (1973-02-01), Eblovi
patent: 3755750 (1973-08-01), Heberling
patent: 3860913 (1975-01-01), Weeks, Jr. et al.

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