Carrier coupler for thyristor-based semiconductor device

Details Carrier coupler for thyristor-based semiconductor device Carrier coupler for thyristor-based semiconductor device

2002-10-28

2004-06-29

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

With switching speed enhancement means

C257S133000, C257S155000, C257S163000, C365S180000

Reexamination Certificate

active

06756612

ABSTRACT:

FIELD OF THE INVENTION
The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices having thyristor-based devices.
BACKGROUND
Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density
0
has benefits including low price), with DRAM cell size being typically between 6 F
2
and 8 F
2
, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density and is typically between about 60 F
2
and 100 F
2
.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin capacitively-coupled thyristor-type NDR device can be effective in overcoming many previously unresolved problems for thyristor-based applications. An important consideration in the design of the thin capacitively-coupled thyristor device involves designing the body of the thyristor sufficiently thin, so that the capacitive coupling between the control port and the thyristor base region can substantially modulate the potential of the base region. Another important consideration in semiconductor device design, including those employing thin capacitively-coupled thyristor-type devices, includes forming devices in an arrangement that realizes high density and fast switching attributes. Because of these high-density and speed-related constraints, the thin capacitively-coupled thyristor is a unique type of NDR device that presents many challenges (e.g., versus a power thyristor).
In microprocessor implementations running at relatively fast clock speeds (e.g., speeds in excess of 1 GHz that result in a memory cycle time of about 1 nanosecond), a thin capacitively-coupled thyristor for memory implementations would advantageously have a write cycle time that is on the same order as the microprocessor. However, thyristors typically switch from a low resistance state to a blocking state over a period that is greater than about 1 microsecond. In connection with the present invention, it has been discovered that this relatively slow switching time is related to the time it takes for minority carriers in an emitter region of the thyristor to recombine. In addition, the thyristor will not switch into or stay in its blocking state if the minority charge carriers are not recombined, and uncombined charge carriers can migrate to other devices and adversely affect the operation thereof. Long access times that can result from slow thyristor switching have typically not been an issue in power applications; however, overcoming these timing challenges can benefit a wide variety of thyristor-based applications, including high-speed memory applications and power applications.
These and other considerations have presented challenges to the implementation of such a thin capacitively-coupled thyristor with bulk substrate applications, and in particular with highly-dense applications having an emitter region of the thyristor buried in a doped well region of the substrate.
SUMMARY
The present invention is directed to overcoming the above-mentioned challenges and others related to the types of devices and applications discussed above and in other memory cells. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a thyristor-based semiconductor device includes a carrier coupler that drains carriers that accumulate in a well region adjacent to a buried emitter region of a thyristor as a result of carrier drainage from the buried emitter region. The carrier drainage reduces the lifetime of carriers in the buried emitter region, which in turn increases the speed at which the thyristor can switch between blocking and conducting states. In addition, the carrier coupler drains carriers that may otherwise migrate to other circuitry adjacent to the thyristor and cause problems therein. With this approach, challenges to the implementation of such devices, including those discussed above, can be addressed.
In another example embodiment of the present invention, a thyristor-based memory cell includes a carrier coupler, such as the one discussed above, which drains carriers from a well region adjacent to an emitter region of the thyristor. The memory cell includes a substrate with a thyristor body having a first doped emitter region buried in a doped well region of the substrate. The first doped emitter region and the well region are of opposite polarity, and the doped well region is susceptible to carrier accumulation via carrier drainage from the doped emitter region. A first base region is coupled between the first doped emitter region and a second base region, and the second base region is coupled between the first base region and a second doped emitter region. The first doped emitter region is electrically coupled to a reference voltage signal. A pass device (e.g., a transistor) is electrically coupled between a bit line and the second doped emitter region and electrically couples the bit line to the second doped emitter region in response to a signal applied thereto. A control port is disposed adjacent to the second base region and is adapted to capacitively cou

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