Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-05-28
2001-11-06
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06313651
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor manufacture, and more particularly to an improved semiconductor carrier and system for temporarily packaging and testing bumped semiconductor components including dice and chip scale packages.
BACKGROUND OF THE INVENTION
Unpackaged semiconductor dice can be burned-in and tested prior to shipment by semiconductor manufacturers. One test procedure involves placing one or more dice in a temporary carrier. The temporary carrier provides a package for handling and electrically connecting the dice to a burn-in board or other testing equipment.
One consideration in designing temporary semiconductor carriers is the size and outline thereof. Preferably a temporary carrier has an outline, or footprint, in the x-y plane that is as small as possible. In addition, the height of a temporary carrier in the “z” direction is preferably as low as possible. With a small outline and low height, a temporary carrier can be handled by standard test equipment used for testing conventional semiconductor packages.
Another consideration in the design of temporary carriers is the ability to transmit electronic test signals to the components under test, at high speeds and with low parasitics. For example, test speeds of 500 mHz or greater are anticipated in future memory devices. In addition, the input/output capability of a temporary carrier is preferably high. This allows test procedures to be performed on components having a large number of input/output paths.
Yet another consideration in the design of temporary carriers is the ability to assemble and disassemble the temporary carriers in a production environment. Preferably a temporary carrier has the capability of being easily assembled, and reliable electrical connections made without damaging the components being tested. In addition, a temporary carrier must be capable of disassembly without damaging the components. Solder contact bumps on unpackaged dice are particularly susceptible to damage and often require a solder reflow step in order to return the bump to a shape suitable for bonding.
Another recent development in semiconductor manufacture involves packaging bare dice in “chip scale” packages. Chip scale packages are also referred to as “chip size” packages, and the dice are referred to as being “minimally packaged”. Chip scale packages can also be constructed in “uncased” or “cased” configurations. Uncased chip scale packages have a peripheral outline that is about the same as an unpackaged die. Cased chip scale packages have a peripheral outline that is slightly larger that an unpackaged die.
Typically, a chip scale package includes a substrate formed of plastic, ceramic, or other electrically insulating material bonded to the face of the die. The substrate includes the external contacts for making outside electrical connections to the chip scale package. For example, the external contacts for a chip scale package can comprise contact bumps arranged in a ball grid array (BGA) Alternately the external contacts can be pads arranged in a land grid array (LGA), or pins in a pin grid array (PGA).
One consideration in temporarily packaging chip scale packages for test and burn-in, is making temporary electrical connections with dense arrays of external contacts. In particular, the external contacts can vary in size between different chip scale packages, and also between external contacts on the same chip scale package. In addition, the external contacts can vary in their location along x, y and z directions. Still further, the location of the external contacts with respect to the outline of the chip scale package can also vary. Typically, “cased” chip scale packages are formed with a standard x-y-z convention which can aid in the alignment process. However, “uncased” chip scale packages can vary in peripheral size and in the locations of the external contacts.
In view of the foregoing, improved carriers for testing bumped semiconductor components including unpackaged dice, and chip scale packages are needed. In particular carriers which can be used to test either dice or packages, using standard testing equipment are needed. In addition, improved methods for aligning and electrically contacting external contacts on temporarily packaged dice and chip scale packages are needed.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved semiconductor carrier and system are provided. The carrier and system are configured for temporarily packaging and testing bumped semiconductor components, such as bare dice, and chip scale packages, having external contacts in the form of contact bumps.
The semiconductor carrier, broadly stated, comprises: a base for retaining one or more semiconductor components; an interconnect mounted to the base including contact members for electrically contacting the semiconductor components; and
a force applying mechanism for biasing the components against the interconnect.
The base can include a separate substrate attached thereto, having dense array external contacts, such as metal balls in a ball grid array (BGA). The dense array external contacts permit a high input/output capability through a mating test apparatus, such as a burn-in board. The base can also be configured for mating electrical engagement with a socket connectable to a test apparatus. In this embodiment the base can comprise ceramic or other insulating material having plated indentations configured to electrically contact spring loaded connectors on the socket.
The semiconductor carrier can also include an alignment member having a peripheral opening configured to align the semiconductor components with the interconnect. The alignment member can comprise an etched plate, or alternately a deposited and patterned layer of resist. In addition, alignment can be performed in stages with a coarse alignment member and a separate fine alignment member. In the plate embodiment, the alignment member can be configured to protect bonded electrical connections (e.g., wire bonds, solder bonds) between the interconnect and base.
The interconnect includes a substrate, such as silicon, ceramic, or FR-4, having integrally formed contact members. The contact members, in addition to electrically contacting the contact bumps on the semiconductor components, can also perform an alignment function by self centering the component to the interconnect. In illustrative embodiments, the contact members comprise: recesses covered with conductive layers; recesses having internal blades; projections configured to retain individual contact bumps; projections configured to electrically engage multiple contact bumps; projections configured to penetrate individual contact bumps; and flat pads configured to contact individual contact bumps.
One or more contact members on the interconnect can have a different configuration to allow orientation verification. In particular, a contact member can be a “Pin 1” indicator, configured to form distinctive “witness marks” on a particular contact bump. In other alternate embodiments, the contact members can be formed on a multi layered flex circuit, similar to TAB tape. In these embodiments the flex circuit can be directly bonded to the conductors on the base. In addition, the flex circuit can include a voltage or ground plane for matching an impedance of the conductors on the flex circuit to other system components.
The force applying mechanism can include one or more biasing members, such as springs or compressible elastomeric pads, for biasing the semiconductor components against the interconnect. In addition, a biasing member can be mounted between the interconnect and base to provide additional compliancy and compressibility for the contact members.
REFERENCES:
patent: 4288841 (1981-09-01), Gogal
patent: 4554505 (1985-11-01), Zachry
patent: 4760335 (1988-07-01), Lindberg
patent: 4937653 (1990-06-01), Blonder et al.
patent: 5006792 (1991-04-01), Malhi et al.
patent: 5046239 (1991-09-01), Miller et al.
patent: 5073117 (1991-12-01), Malhi et al.
patent: 50
Akram Salman
Farnworth Warren M.
Gochnour Derek
Hembree David R.
Wood Alan G.
Gratton Stephen A.
Karlsen Ernest
Micro)n Technology, Inc.
Tang Minh
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