Registers – Coded record sensors – Error checking
Reexamination Certificate
2001-07-27
2003-12-02
Frech, Karl D. (Department: 2876)
Registers
Coded record sensors
Error checking
Reexamination Certificate
active
06655588
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a card system, and an integrated circuit (IC) card and a card reader/writer both used for the card system. In particular, the present invention relates to a card system in which an IC card, such as a JAVA card which is capable of transmitting and receiving data at a high rate, and a card reader/writer are used.
The present invention relates to a card system, and an IC card and a card reader/writer both used for the card system. In particular, the present invention relates to a card system in which a card, such as a JAVA card which is capable of transmitting and receiving data at a high rate is used, and an IC card and a card reader/writer used for the card system.
BACKGROUND OF THE INVENTION
Magnetic cards have heretofore been used for many of the cash cards and the credit cards. Recently, counterfeiting of magnetic cards has been increased. Employing an IC card in lieu of a magnetic card has attracted attention. An IC card has an internal CPU for processing encryption and decipherment so that counterfeiting of the IC card is more difficult in comparison with the magnetic card. Much information can be stored in an IC card, and hence many of the IC cards are equipped with multi-functions.
A conventional card system will be described with reference to
FIG. 1
which illustrates a diagram of a IC card system to which the present invention is applied.
FIG. 1
illustrates a diagram showing structures of an IC card
10
and an IC card reader/writer
20
for reading information from the IC card
10
and/or recording information on the IC card
10
. The IC card reader/writer
20
comprises a port terminal (PORT)
22
from and to which data is input and output, a clock terminal (CLOCK)
23
for outputting a clock signal for counting input and output timings of data, a reset terminal (RESET)
24
for outputting a reset signal which initiates operation of a CPU
11
located in the IC card
10
, a power supply terminal (V
DD
)
25
for supplying power to drive the CPU
11
in the IC card
10
and a ground terminal (GND)
26
.
The IC card reader/writer
20
further comprises a CPU
28
for controlling various signals which are output to terminals
22
to
26
, a power supply
21
for driving the CPU
28
and a pull-up resistor
27
connected between the power supply
21
and the port terminal
22
. The IC card
10
comprises terminals
12
to
16
which correspond to the terminals
22
to
26
of the IC card reader/writer
20
, respectively, through which various signals are input to and output from the IC card
10
. The IC card
10
further comprises a memory
17
for storing a program for carrying out half-duplex synchronous communication and user data, and a CPU
11
for executing the program stored in the memory
17
.
A term “half-duplex” used herein means a communication scheme for alternatingly transmitting data between two communication equipments to enable bi-directional communications. When one of the equipments transmits data, another equipment receives the data. Simultaneous transmission of data by both equipments is not allowed. For example, when data is output from the IC card reader/writer
20
, the IC card
10
can not output data to the IC card reader/writer
20
and only receives data from the IC card reader/writer
20
.
Operation of a system shown in
FIG. 1
will be described. When the IC card
10
is mounted to the IC card reader/writer
20
, power VDD is supplied to a main body of the IC card
10
through the power supply terminals
25
and
15
in response to an instruction from the CPU
28
. More specifically, when the power supply terminal
25
and the ground terminal
26
are electrically connected with the power supply terminal
15
and the ground terminal
16
, respectively, the CPU
11
is enabled to be driven.
Thereafter, a reset signal is output from the IC card reader/writer
20
via the reset terminal
24
in accordance with an instruction from the CPU
28
. Then, a reset signal is supplied to the IC card
10
via the reset terminal
14
and in turn provided to the CPU
11
. This brings the CPU
11
into such a state that the CPU
11
can be initiated to operate.
Subsequently, the IC card reader/writer
20
outputs a clock signal via the clock terminal
23
in accordance with an instruction from the CPU
28
. Then, the output clock is provided to the CPU
11
of the IC card
10
via the clock terminal
13
. Then, IC card reader/writer
20
outputs a data read request, and data which is to be written into the IC card
10
, via the port terminal
22
in synchronization with a clock signal being output.
On the IC card
10
, the CPU
11
reads out user data stored in the memory
17
to output the user data to the IC card reader/writer
20
, and writes data supplied from the IC card reader/writer
20
into the memory
17
based upon the request and data which have been received by the IC card
10
in accordance with a scheme of half-duplex synchronous communication.
FIGS. 8 and 9
illustrate data formats used for the half-duplex synchronous communication.
FIG. 8
illustrates data format when data communication is normally conducted and
FIG. 9
illustrates data format when data communication is not normally conducted.
As shown in
FIG. 8
, a start bit which informs of transmission of data bits, data bits D
0
through D
7
which constitute substantially transmitted and received data and a parity bit from which it is checked whether the data has been correctly transferred are transmitted between the IC card reader/writer
20
and the IC card
10
.
When the data communication has not been normally conducted as shown in
FIG. 9
, a data retransmission request signal is transmitted between the IC card reader/writer
20
and the IC card
10
for requesting a transmitting side to retransmit the data. In
FIGS. 8 and 9
, the clock signal comprises, for example, 512 pulses in each period. Each data transmitted and received at a V
DD
level or a Ground level.
The IC card reader/writer
20
and IC card
10
are controlled by the CPUs
28
and
11
, so that each of the IC card reader/writer
20
and IC card
10
is brought in a state of an output mode for transmitting data or an input mode for receiving data, whilst both of the IC card reader/writer
20
and IC card
10
are not simultaneously brought into the output mode in order to carry out half-duplex data communication.
Operations of the IC card reader/writer
20
and the IC card
10
when data is normally transmitted from the IC card reader/writer
20
to the IC card
10
will be described.
As shown in
FIG. 8
, the IC card reader/writer
20
which is functioning as a data transmitting side in half-duplex communication is controlled by the CPU
28
so that it is brought into the output mode in periods T
0
to T
9
and input mode and in periods T
10
and T
11
, respectively. More specifically,
(1) a start bit is transmitted in the beginning of T
0
.
(2) Data bits D
0
to D
7
are transmitted at T
1
to T
8
, respectively.
(3) At T
9
, a parity bit having “0” or “1” which is determined depending upon data bits is transmitted.
(4) When a data retransmission request signal is transmitted at T
10
and T
11
, the IC card reader/writer
20
is controlled to be able to receive the signal.
The IC card
10
which is functioning as a data receiving side in half-duplex communication is controlled so that it is brought into the input mode at all periods T
0
to T
11
. More specifically,
(1) a start bit is received at T
0
.
(2) Data bits are received at T
1
to T
8
.
(3) A parity bit is received at T
9
.
(4) The IC card
10
executes parity check with reference to the parity which has been received at T
10
, and T
11
. Since no error occurs, no data retransmission request signal is transmitted and information comprised of data bits D
0
to D
7
is stored in the memory
17
.
Thus, the IC card reader/writer
20
functioning as a data transmitting side and the IC card
10
functioning as a data receiving side are brought into the input mode at periods T
10
and T
11
, and the p
Caputo Lisa M.
Frech Karl D.
NEC Electronics Corporation
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