Card manufacturing technique and resulting card

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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C438S107000

Reexamination Certificate

active

07022547

ABSTRACT:
A card manufacturing technique and the resulting card are provided. The card has a ground and/or power layer extending to the edges of a circuit board for electrostatic discharge protection but also has gaps at the edge of the ground and/or power layer to avoid short circuiting with conductive segments of another layer deformed when the card is trimmed during manufacture.

REFERENCES:
patent: 5942794 (1999-08-01), Okumura et al.
patent: 5969416 (1999-10-01), Kim
patent: 6040622 (2000-03-01), Wallace
patent: 6507117 (2003-01-01), Hikita et al.
patent: 0340492 (1989-11-01), None
patent: 1290800 (1972-09-01), None
Patent Abstracts of Japan, vol. 1998, No. 14, Dec. 31, 1998 & JP 10 242608 A, Sep. 11, 1998, abstract.
Hosseini, S.: “The Electrical Insulation of Electroplating Bus Bars in Flexes,” Motorola Inc., Schaumburg, Illiniois, vol. 15, May 1, 1992, p. 39.
Patent Abstracts of Japan, vol. 016, No. 364, Aug. 6, 1992 & JP 04 114490 A, Apr. 15, 1992, abstract.
Patent Abstracts of Japan, vol. 014, No. 082, Feb. 15, 1990 & JP 01 295476 A, Nov. 29, 1989, abstract.
International Search Report mailed Oct. 30, 2002.

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