Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device
Reexamination Certificate
2002-09-17
2004-01-13
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
C257S023000, C257S183000, C257S197000, C257S557000
Reexamination Certificate
active
06677624
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transistor, and more particularly, to a junction type transistor of carbon nanotubes.
2. Discussion of the Background Art
There are a horizontal, and vertical types in background art junction type transistors. The background art junction transistor will be explained with reference to the attached drawings.
FIG. 1
a
illustrates a plane view of the background art junction transistor and
FIG. 1
b
illustrates a sectional view of the background art junction transistor.
Referring to
FIGS. 2
a
and
2
b,
there is a background art PNP junction transistor having an n type epitaxial layer
2
isolated by a silicon oxide film
3
formed on a substrate
1
. There are p type impurity regions
4
and
5
at fixed intervals in the n type epitaxial layer
2
, wherein the p type impurity region
4
serves as a collector of a transistor and the p type impurity region
5
serves as an emitter of the transistor.
The aforementioned background art junction transistor has the following problems.
The limitation in fabrication of the background art transistor that an NPN transistor fabrication as well as circuit integration should be done on the same time, a geometry of the background art transistor is not optimal for preventing electron-hole couplings and collecting holes at collectors in a base.
Second, the comparatively high doping concentration in the collector with a thick depletion layer in the base degrades a performance, and conduction of additional diffusion in an effort to overcome such demerit results in a complicated fabrication process.
Third, even though the vertical type junction transistor fabricated in an effort for solving the aforementioned background art problems of the transistor may more or less help in an improvement of the performance, the fabrication of vertical type junction transistor requires significant cost increase and effort since it requires totally different fabrication process.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed a transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a transistor having carbon nanotubes which has improved performances and simple fabrication process.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the transistor of carbon nanotubes includes a base having a bundle of (n,n) carbon nanotubes, and an emitter and a collector having (n,m, n−m≠3 l) nanotubes connected to opposite sides of the base respectively.
A single carbon nanotube has a diameter not greater than approximately 1 nm, is metallic or semiconductive depending on atomic array of the carbon in the tube, and can be doped with p type impurities, but not with n type impurities.
A bundle of a few tens of metallic carbon nanotubes forms a so called pseudo gap with an electron and a hole present on the same time. Upon application of a bias to such a nanotube bundle, electrons or holes are caused to enter more or to enter less even if not doped with impurities.
Accordingly, in the transistor of carbon nanotubes of the present invention, a bundle of carbon nanotube is used as a base part of the transistor, one single line or a few lines of carbon nanotubes are used as the emitter and the collector, respectively.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5973444 (1999-10-01), Xu et al.
patent: 6280677 (2001-08-01), Yakobson
patent: 6325904 (2001-12-01), Peeters
Andrea Thess, et al. “Crystalline Ropes of Metallic Carbon Nanotubes;” Nature, vol. 273, Jul. 26, 1996 pp. 483-487.
D.S. Bethune, et al. “Cobalt-catalysed growth of carbon nanotubes with single-atomic-layer walls;” Nature, vol. 363, Jun. 17, 1993, pp. 605-607.
M.S. Dresselhaus, “New tricks with nanotubes;” Nature, vol. 391, Jan. 1, 1998; pp. 19-20.
Jeroen W.G. Wildoer, et al., “Electronic structure of atomically resolved carbon nanotubes;” Nature, vol. 391, Jan. 1, 1998; pp. 59-64.
Paul Delaney, et al., “Broken symmetry and pseudogaps in ropes of carbon nanotubes;” Nature, vol. 391, Jan. 29, 1998; pp. 466-468.
Tans, et al. “Room-Temperature Transistor Based On A Single Carbon Nanotube,” Nature, vol. 393, May 7, 1998, pp. 49-52.
Bochrath et al., Science, vol. 275, pp. 1922-1925, Mar., 1997.
Fleshner & Kim LLP
Hyundai Electronics Industries Co,. Ltd.
Tran Mai-Huong
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