Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-08-28
2002-05-14
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S753000, C257S767000
Reexamination Certificate
active
06388328
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to integrated electronic circuits. More specifically, the present invention relates to an interconnect system for an integrated circuit and a method of fabricating the interconnect system.
(2) Description of the Related Art
Modern integrated circuits are generally made up of millions of active and passive devices such as transistors, capacitors, and resistors disposed onto a silicon wafer. These devices are initially isolated from one another, but are later interconnected together by an interconnect system to form functional circuits. The quality of the interconnect system drastically affects the performance and reliability of the fabricated circuit.
An interconnect system typically includes metal lines, spaced apart from each other, which interconnect the various active and passive devices found in a silicon wafer onto which the interconnect system had been deposited and fabricated. Insulating dielectric layers are deposited between the metal lines for isolating the metal lines from one another. Inherent in the structure of the interconnect system is a capacitance associated with the metal lines spaced apart from each other. As the capacitance is to first order inversely proportional with the distance between the metal lines, one way to reduce the capacitance between two lines would be to increase the space between the lines. However, this option is limited by the integration capacity of the integrated circuit.
A preferable way to reduce the capacitance between two lines of the interconnect system is to reduce the dielectric constant k of the dielectric material deposited between the metal lines, as the capacitance is directly proportional to the dielectric constant of the dielectric material between the metal lines. Typically, interconnect systems use a dielectric material such as Silicon Dioxide (SiO
2
). The dielectric constant of SiO
2
is approximately 4. Other dielectric materials can be used such as Silicon Oxifluoride (SiOF) with a dielectric constant of 3-3.5, or Aerogel which is a foam with vacuum or air pores with a dielectric constant which can approach the dielectric constant of air, i.e., 1. The problem with dielectric materials having lower dielectric constants is that they may not adequately support the structure of the interconnect system as these materials have a relatively high Young's modulus which makes them relatively soft, especially for materials with the dielectric constant k<2.
FIG. 1
shows a cross-sectional view of an interconnect system
100
. The interconnect system
1
has a substrate
2
which typically includes active and passive electronic structures. An insulating layer
4
is deposited over substrate
2
. The insulating layer
4
is made of a dielectric material which provides electrical insulation between the substrate
2
and any other electrically conductive layer deposited upon layer
4
. Layer
4
could be, by way of non-limiting example, silicon dioxide (SiO
2
) either doped or undoped, silicon nitride (Si
3
N
4
) or silicon oxinitride (SiO
x
N
y
). Following the deposition of the insulating layer
4
a metal layer is deposited thereon. Electrically conductive interconnect lines
10
are then formed by etching out selected portions of the metal layer. The electrically conductive interconnect lines
10
serve the purpose of interconnecting various electronic devices, active or passive, which reside in the substrate
2
. The interconnect lines
10
are spaced apart from each other in order not to short circuit the various devices to which the interconnect lines are connected. The space between interconnect lines
10
is typically filled with a dielectric material
8
which is deposited upon interconnect lines
10
forming the pattern shown in
FIG. 1. A
second electrically conductive layer of interconnect lines
26
is formed over the dielectric layer
8
in a direction usually orthogonal to the direction of the interconnect lines
10
. Continuing the above process, more insulating layers followed by conducting layers could be deposited to finally form the interconnect system.
The interconnect system illustrated in
FIG. 1
uses SiO
2
for the dielectric layer
8
. While this type of material can provide the mechanical support necessary to withstand the stress of the structures deposited thereupon, the resulting large capacitance between lines, due to the relatively high dielectric constant of SiO
2
, makes this material less and less desirable in the high performance interconnect systems of the future.
FIG. 2
shows a cross sectional view of an interconnect system
200
wherein the dielectric layer
8
has been applied over interconnect lines
10
so as not to fill out completely the gaps between the interconnect lines
10
and, thus, to provide for air gaps
16
between the interconnect lines
10
. However, due to the nature of the structure of the interconnect system and of the various processes for deposition of the dielectric layer
8
, which include physical deposition, chemical vapor deposition, and plasma deposition, a certain amount of the dielectric is incorporated between the metal lines
10
. As one can see, the dielectric material
8
is still deposited between the metal lines
10
leaving small voids
16
. This is undesirable as the dielectric constant and thus the capacitance between the adjacent lines increases with the amount of dielectric material between the lines.
It is desirable to provide for an interconnect system wherein the space between the interconnect lines has a dielectric constant as low as possible and substantially uniform throughout that space.
BRIEF SUMMARY OF THE INVENTION
An interconnect system is disclosed. The interconnect system according to the present invention includes a substrate and a first dielectric layer formed upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. The at least two electrically conductive interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal with 1. A dielectric film is bonded onto the top surfaces of the at least two interconnect lines. The dielectric film substantially prevents obstruction, by further process, of the space formed between the two adjacent side surfaces of the two adjacent interconnect lines.
REFERENCES:
patent: 5112761 (1992-05-01), Matthews
patent: 5257162 (1993-10-01), Crafts
patent: 5289035 (1994-02-01), Bost et al.
patent: 5289337 (1994-02-01), Aghazadeh et al.
patent: 5414221 (1995-05-01), Gardner
patent: 5431863 (1995-07-01), Mochizuki et al.
patent: 5476817 (1995-12-01), Numata
patent: 5624868 (1997-04-01), Iyer
patent: 5665644 (1997-09-01), Sandhu et al.
patent: 5690749 (1997-11-01), Lee
patent: 5751056 (1998-05-01), Numata
patent: 5814888 (1998-09-01), Nishioka et al.
patent: 6-97300 (1994-04-01), None
Doyle Brian
Vu Quat T.
Yau Leopold
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Loke Steven
Vu Hung Kim
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