Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2011-07-19
2011-07-19
Pham, Hoai v (Department: 2892)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S460000, C257SE21499
Reexamination Certificate
active
07981723
ABSTRACT:
A capped wafer includes a device wafer and an opposing cap wafer with an annular glass frit disposed between the device wafer and the cap wafer. The glass frit and the opposing wafers define a sealed volume that encloses the capped devices, and the glass frit may support the wafer cap during removal of excess wafer cap material from the capped wafer. A method of fabricating a capped wafer includes fabricating an annular intermediate layer between a device wafer and a cap wafer. In an alternate embodiment, a plurality of unsingulated dice each contains bond pads along a single edge and are arranged on a device wafer in an alternating order so that the bond pads of a first die are adjacent to the bond pads of a second die. Removing excess cap wafer material involves making a first cut in the cap wafer near a first row of bond pads and a second cut near the adjacent row of bond pads, such that a strip of wafer cap material is suspended from portions of an underlying supporting member near the edge of the capped wafer, and then removing the wafer cap material suspended from the portions of the supporting glass frit using an adhesive tape.
REFERENCES:
patent: 6483160 (2002-11-01), Engelhardt et al.
patent: 6893574 (2005-05-01), Felton et al.
patent: 6946366 (2005-09-01), Spooner et al.
patent: 2003/0075794 (2003-04-01), Felton et al.
Bhagavat Milind
Tarvin Erik
Yang Xue'en
Analog Devices Inc.
Pham Hoai v
Sunstein Kann Murphy & Timbers LLP
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