Capped solder bumps which form an interconnection with a tailore

Details Capped solder bumps which form an interconnection with a tailore Capped solder bumps which form an interconnection with a tailore

1999-03-11

2000-10-03

Bowers, Charles

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

438614, 438615, 438658, 438660, 438661, 257737, 257738, H01L 2144, H01L 2348

Patent

active

061277312

ABSTRACT:
The melting point of the solder forming a controlled collapse chip connection is tailored by forming a thin metal cap of a metal such as palladium or silver on a solder bump. When the solder bump is melted during reflow, the metal cap dissolves into the solder. Because the resulting alloy has a higher melting point than the solder, subsequent reflow processing does not melt the chip join structure.

REFERENCES:
patent: 5391514 (1995-02-01), Gall et al.
patent: 5729896 (1998-03-01), Dalal et al.
patent: 5776790 (1998-07-01), Starr et al.
patent: 5794839 (1998-08-01), Kimura et al.
patent: 5796591 (1998-08-01), Dalal et al.
patent: 5834366 (1998-11-01), Akram
patent: 5838069 (1998-11-01), Itai et al.

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