Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2007-03-13
2007-03-13
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Interconnection arrangements
C365S072000, C365S230030, C365S244000
Reexamination Certificate
active
11166586
ABSTRACT:
Two memory areas on a wafer are coupled through pass transistors to double the memory capacity of each area and can be sawed to yield two memory chips each with single memory area. A pair of pass transistors are used to couple each dedicated functional pad in both memory areas, when the pass transistors are turned on. The connection between the pass transistor pair can be sawed through to yield single capacity memory dice. The memory capacity can be further increased by coupling more memory areas together with pass transistors.
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Chang Ling-Yueh
Chung Pwu-Yueh
Hung Chi-Cheng
Lin Patent Agent H. C.
Lyontek Inc.
Pham Ly Duy
Zarabian Amir
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