Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1997-04-21
2001-03-06
Tran, Minh Loan (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S296000, C257S689000
Reexamination Certificate
active
06198153
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the art of manufacturing electrical components. In particular, the present invention relates to the art of fabricating capacitors.
2. Description of Related Art
The conventional method for fabricating capacitors on semiconductors using analog fabrication process technology is relatively simple because the analog fabrication process involves the use of two polysilicon layers. In the analog process, as illustrated by
FIG. 1
, the capacitors are fabricated using a two polysilicon layers. In
FIG. 1
, the first layer
12
of polysilicon forms the “Bottom Plate” of the capacitor while the second layer
10
of polysilicon forms the “Top Plate” of the capacitor
8
. In addition, because the capacitance per unit area of the polysilicon-polysilicon type of capacitors is relatively large, the physical area required by such capacitors is relatively small.
Fabrication of capacitors on semiconductors is difficult when the digital circuit fabrication process technology is used because the digital process does not utilize multiple polysilicon layers. Therefore, the conventional method of fabricating capacitors for a digital process involves the use of metal layers as the plates of the capacitors. As illustrated by
FIG. 2
, a conventional capacitor in a digital process comprises a metal top plate
14
, sandwiched between two metal bottom plates
16
and
18
.
Because the capacitance per unit area of the metal-metal type of capacitors is relatively small, the physical area required by such capacitors is relatively large. In an effort to reduce the physical area occupied by the metal-metal capacitors, the capacitor
20
illustrated by
FIG. 2
has the top plate
14
being sandwiched between two bottom plates
16
and
18
which are connected
17
to each other. This structure doubles the surface area between the top plate
14
and the bottom plates
16
and
18
compared to the surface area of capacitors having the more typical structure of one top plate and one bottom plate.
However, even with the use of the sandwich technique, the metal-metal capacitors occupy larger physical areas compared to the polysilicon-polysilicon capacitors of the same capacitance. Due to their larger size, the metal-metal capacitors introduce greater levels of noise to the substrate
22
compared to the polysilicon-polysilicon capacitors, and also are more easily affected by the substrate noise.
SUMMARY OF THE INVENTION
To reduce the noise effects of metal-metal capacitors to and from the substrate, the present invention discloses a three layer metal capacitor structure with a fourth, polysilicon layer, fabricated between the metal plates and the substrate.
The present invention provides for fabricating a capacitor formed on a semiconductor. The capacitor comprises a top plate, a bottom plate, and a shielding layer between said bottom plate and the semiconductor.
The plates of the capacitor may be metal. The bottom plate of the capacitor may comprise a first portion and a second portion, with the two portions sandwiching the top plate. This is done to increase the surface area between the top and the bottom plates. In the preferred embodiment, the plates are made of metal and the shielding layer is made from a polysilicon or silicized polysilicon. The capacitor of the present invention is most useful in Complementary Metal Oxide Semiconductor (CMOS) semiconductor chips.
Also provided by the present invention is a method of fabricating a capacitor in a digital CMOS process. The method is to layer the shielding polysilicon layer first, then fabricate the capacitor metal layers on the top of the shielding layer. This design separates the capacitor from the substrate of the semiconductor to reduce noise coupling.
These and other aspects, features, and advantages of the present invention will be apparent to those persons having ordinary skilled in the art to which the present invention relates from the foregoing description and the accompanying drawings.
REFERENCES:
patent: 5104822 (1992-04-01), Butler
patent: 5135883 (1992-08-01), Bae et al.
patent: 5206788 (1993-04-01), Larson et al.
patent: 5220483 (1993-06-01), Scott
patent: 5225704 (1993-07-01), Wakamiya et al.
patent: 5548474 (1996-08-01), Chen et al.
patent: 5576925 (1996-11-01), Gorowitz et al.
patent: 5684315 (1997-11-01), Uchiyama et al.
patent: 5724107 (1998-03-01), Nishikawa et al.
patent: 402047862 (1990-02-01), None
IBM Technical Disclosure Bulletin vol. 17, No. 6, Nov. 1974.
Liu Edward W.
Wong See-Hoi Caesar
LSI Logic Corporation
Mitchell Silberberg & Knupp LLP
Nguyen Cjong Q
Tran Minh Loan
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