Capacitorless 1-transistor DRAM cell and fabrication method

Details Capacitorless 1-transistor DRAM cell and fabrication method Capacitorless 1-transistor DRAM cell and fabrication method

2006-04-25

2006-04-25

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Amorphous semiconductor material

C257S061000, C257S062000, C257S068000, C257S069000, C257S070000, C257S071000, C257S296000, C257S329000, C257S906000

Reexamination Certificate

active

07034336

ABSTRACT:
The channel region (11) and the source-drain regions (9, 10) are arranged vertically at a sidewall of a dielectric trench filling (4). On the opposite side, the semiconductor material is bounded by the gate dielectric (18) and the gate electrode (16), which is arranged in a cutout of the semiconductor material. A memory cell array comprises a multiplicity of vertically oriented strip-type semiconductor regions in which source-drain regions are implanted at the top and bottom and a channel region embedded in insulating material on all sides is present in between as a floating body.

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Wann, H., et al., “A Capacitorless DRAM Cell on SOI Substrate,” 1993 IEEE, pp. 635-638.
Okhonin, S., et al., “A SOI Capacitor-less 1T-DRAM Concept,” 2001 IEEE International SOI Conference.

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