Capacitor trench-top dielectric for self-aligned device...

Details Capacitor trench-top dielectric for self-aligned device... Capacitor trench-top dielectric for self-aligned device...

1999-03-17

2001-02-06

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S430000, C438S243000, C438S244000

Reexamination Certificate

active

06184107

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to semiconductor devices. In particular, the present invention relates to dynamic random access memory (DRAM) devices.
BACKGROUND OF THE INVENTION
Increasing numbers of semiconductor devices, such as individual memory cells, are being created on a single chip. As a result, dimensions of the devices continue to shrink. Shrinking device dimensions can increase the difficulty of ensuring proper alignment over an adequate functional area of the structures included in the semiconductor devices.
For example, a merged isolation node trench (MINT) cell is illustrated in FIG.
1
. The MINT cell illustrated in
FIG. 1
includes a planar transfer device. The device shown in
FIG. 1
includes a deep trench capacitor
1
a shallow trench isolation region
2
used to define the active area, a bit line contact (CB)
3
, a word line (WL)
5
, or transfer device gate, gate oxide
7
and N+ source/drain regions
9
and
11
. In the structure illustrated in
FIG. 1
, a buried strap
12
connects the deep trench capacitor storage trench node
1
to the source/drain diffusion
11
of the transfer device. In a MINT cell, MINT buried strap resistance may be a function of the overlap of the deep trench
1
and the shallow trench isolation region
2
of the memory cell.
SUMMARY OF THE INVENTION
The invention addresses MINT buried strap resistance as a function of overlay between the deep trench and active area overlay making the shallow trench isolation pattern self-aligned to the deep trench to ensure full trench width for buried strap formation.
In accordance with these and other objects and advantages, the present invention provides a semiconductor device including a substrate. At least one pair of deep trenches is arranged in the substrate. A collar lines at least a portion of a wall of each deep trench. The trenches contain a conductive fill material. A buried strap extends completely across each trench over each trench fill and each collar. An isolation region is arranged between the deep trenches. A dielectric region overlies each buried strap in each deep trench.
Aspects of the present invention also provide a process for forming an active area and shallow trench isolation self-aligned to a deep trench. The process includes forming at least one pair of adjacent deep trenches in a substrate and through a first dielectric layer on a surface of the substrate. A dielectric collar is provided on at least a portion of a side wall of each deep trench. The deep trenches are filled. A top surface of the deep trench fill is recessed. A portion of the deep trench collars is etched. A strap material is deposited on the deep trench fill and within the recessed deep trench collars. A second dielectric layer is deposited on exposed surfaces of the strap material, the substrate, and the first dielectric layer. The structure is planarized, thereby removing portions of the second dielectric layer, such that the second dielectric layer only remains in the deep trenches. A layer of photoresist is deposited. The photoresist is patterned to expose portions of the second dielectric layer in the deep trenches and portions of the first dielectric layer such that at least a portion of the photoresist remains overlapping the deep trench. Portions of the first dielectric layer between the trenches are selectively removed. A portion of the second dielectric layer in the trenches and a portion of the substrate between the trenches are selectively removed. A third dielectric layer is deposited in spaces created by removal of the portions of the first dielectric layer and portions of the second dielectric layer. The third dielectric layer is then planarized. Remaining portions of the first dielectric layer are removed.
Further aspects of the present invention provide a semiconductor device formed by the above process.
Still other objects and advantages of the present invention will become readily apparent by those skilled in the art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not as restrictive.


REFERENCES:
patent: 5831301 (2000-06-01), Horak et al.
patent: 5945707 (1999-08-01), Bronner et al.
patent: 6074909 (2000-06-01), Gruening

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