Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-07-14
2001-09-11
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S240000
Reexamination Certificate
active
06287934
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a capacitor structure in a semiconductor memory cell using a ferroelectric thin film and a method for fabricating such a capacitor structure. More particularly, the invention relates to a capacitor structure in a semiconductor memory cell made of a nonvolatile memory cell using a ferroelectric thin film (so-called FERAM) or DRAM, and a method for fabricating such a capacitor structure.
2. Description of the Related Art
Along with the recent progress in film-making technologies, active studies are being made for applications non-volatile memory devices using ferroelectric thin films. Nonvolatile memory utilizes high-speed polarization inversion and residual polarization in a ferroelectric thin film to enable high-speed rewriting. Nonvolatile memory devices using a ferroelectric thin film currently under studies can be classified into two systems, one for detecting changes in amount of stored charge in the ferroelectric capacitor and the other for detecting changes in resistance of the semiconductor by spontaneous polarization in the ferroelectric film. The semiconductor memory cell intended by the present invention belongs to the former system.
A nonvolatile semiconductor memory cell of the system relying on detecting changes in amount of stored charge in the ferroelectric capacitor is basically made of a ferroelectric capacitor and a select transistor. The ferroelectric capacitor is made up from, for example, a lower electrode, an upper electrode and a ferroelectric thin film sandwiched between the electrodes. Data writing and reading in the nonvolatile memory cell of this type are effected by using P-E hysteresis loop of the ferroelectric element as shown in FIG.
1
. When an external field applied to the ferroelectric film is removed, spontaneous polarization occurs in the ferroelectric film. Residual polarization of the ferroelectric film exhibits +P
r
when a plus external field is applied, and −P
r
when a minus external field is applied. The state where the residual polarization is +P
r
(D in
FIG. 1
) is referred to as “0”, and the state where the residual polarization is −P
r
(A in
FIG. 1
) is referred to as “1”.
In order to distinguish the state of “1” or “0”, a plus external field, for example, is applied to the ferroelectric thin film. Then, polarization of the ferroelectric film exhibits the state of “C” of FIG.
1
. In this case, if data is “0”, then the state of polarization in the ferroelectric thin film changes from D to C. On the other hand, if data is “1”, the state of polarization in the ferroelectric thin film changes from A through B to C. When data is “0”, polarization inversion of the ferroelectric thin film does not occur. When data is “1”, polarization inversion occurs in the ferroelectric thin film. As a result, a difference is produced in amount of stored charge of the ferroelectric capacitor. By activating the select transistor of a selected memory cell, the stored charge is detected as a bit-line potential. When the external field is changed to 0 after reading data, the state of polarization in the ferroelectric thin film is changed to state D of
FIG. 3
regardless of data being “0” or “1”. Therefore, when data is “1”, a minus external field is applied to produce state A through D and E so that data “1” be written reliably.
A sort of such nonvolatile memory (stacked nonvolatile memory) is taught by S. Onishi, et al. in the literature “A Half-Micron Ferroelectric Memory Cell Technology with Stacked Capacitor Structure”, IDEM 94-843. A schematic fragmentary cross-sectional view of the nonvolatile memory cell taught in the literature is shown in FIG.
2
.
In the nonvolatile memory cell having the structure shown in the literature, the top surface of the ferroelectric thin film is partly covered by an insulation film, the area of the upper electrode in contact with the ferroelectric thin film is small. That is, the effective capacitor area is small, and the amount of stored charge is small. Therefore, it is desirable to cover the entirety of the top surface of the ferroelectric thin film with the upper electrode as schematically shown in
FIG. 3
in a fragmentary cross-sectional view. In this case, however, field concentration occurs at corners of the lower electrode. It causes a distortion of the P-E hysteresis loop shown in
FIG. 1
or an increase in leak current, and the existence of corners of the lower electrode invites a deterioration of the capacitor structure.
OBJECTS AND SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a capacitor structure in a semiconductor memory cell ensuring a wide contact area of its upper electrode with a ferroelectric thin film while alleviating local concentration of the electric field in the ferroelectric thin film, and to provide a method for fabricating such a capacitor structure.
According to the invention there is provided a capacitor structure of a semiconductor memory cell, comprising:
(a) a lower electrode formed on a base body;
(b) a capacitor insulation film made of a ferroelectric thin film formed on the lower electrode; and
(c) an upper electrode formed on the capacitor insulation film, the lower electrode having a semi-spherical shape.
The semi-spherical shape not only pertains to a shape obtained by cutting a ball along a plane but also involves other shapes obtained by butting ellipsoids or paraboloids. It further involves any other shapes whose perimetric curves obtained by cutting them along arbitrary vertical planes have differential coefficients of finite values (differential coefficients never being indefinite, or differential coefficients of continuous values). In the present invention, by making the lower electrode in a semi-spherical shape, local concentration of the electric field can be prevented, and the effective area of the capacitor can be increase. The outer contour (in a plan view) of the portion of the lower electrode in contact with the base body may be in form of a circle, oval or corner-rounded rectangle).
In the capacitor structure of the semiconductor memory according to the invention, the top surface of the base body may be in a higher level in its portion underlying the lower electrode than in its other portion near the lower electrode and not covered by the lower electrode, and the capacitor insulation film may be extended to the portion of the base body not covered by and near to the lower electrode. This structure permits a further increase of the capacitor effective area and hence a further increase of the amount of stored charge.
A method for fabricating a capacitor structure of a semiconductor memory cell according to a first aspect of the invention comprises the steps of:
(a) forming a lower electrode on a base body; and
(b) forming a ferroelectric thin film on the entire surface, then forming an electrode thin film on the ferroelectric thin film, subsequently patterning the electrode thin film and the ferroelectric thin film, to form a capacitor insulation film made of the ferroelectric thin film covering the lower electrode, and an upper electrode made of the electrode thin film, wherein the lower electrode has a semi-spherical shape.
A method for fabricating a capacitor structure of a semiconductor memory cell according to a second aspect of the invention comprises the steps of:
(a) forming a lower electrode on a base body;
(b) forming a ferroelectric thin film on the entire surface, and thereafter patterning the ferroelectric thin film, to thereby obtain a capacitor insulation film in form of the ferroelectric thin film covering the lower electrode; and
(c) forming an electrode thin film on the entire surface and then patterning the electrode thin film, to thereby obtain an upper electrode made of the electrode thin film, wherein the lower electrode has a semi-spherical shape.
In the method for fabricating a capacitor structure of a semiconductor memory cell according to either the first aspect or the second aspect of the invention, i
Estrada Michelle
Fourson George
Sonnenschein Nath & Rosenthal
Sony Corporation
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