Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-12-22
2003-05-20
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S396000
Reexamination Certificate
active
06566221
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a capacitor in a DRAM, and more particularly, to a structure of a lower electrode of a capacitor and a method for fabricating the same.
2. Background of the Related Art
In general with a semiconductor memory becoming highly packed following the development of semiconductor memory from the mega class to the giga class, several methods have been employed for increasing an effective area of a capacitor within a restricted area of a cell in the semiconductor memory.
In one method, the effective area of the capacitor is increased by forming a three dimensional storage node, such as a trench type or a cylinder type storage node.
In another method, a surface of a storage electrode used as a lower electrode of the capacitor is formed of so called HSG-Si (Hemispherical Grain-Silicon), which does not have a smooth morphology, but a rugged morphology, for increasing the effective area of the capacitor.
In a further method, the techniques of a three dimensional storage node and HSG-Si are combined.
A related art method for fabricating a capacitor, according to this later method, will be explained with reference to
FIGS. 1A-2D
.
FIGS. 1A-1D
illustrate sections showing the steps of a related art method for fabricating a cylindrical capacitor.
Referring to
FIG. 1A
, an interlayer insulating film
3
is deposited on a semiconductor substrate
1
having an impurity region
2
formed therein, and a portion of the interlayer insulating film
3
over the impurity region
2
is selectively removed to form a contact hole for a capacitor storage electrode. Then, an amorphous silicon layer
4
is deposited over the substrate
1
. The amorphous silicon layer
4
is formed of an amorphous silicon doped with phosphorus at a concentration of approx. 2.0E20 atoms/cm
3
. As shown in
FIG. 1B
, an oxide film
5
is deposited over the substrate
1
, and subjected to photo-etching to remove portions of the oxide film
5
and leave the oxide film
5
in a region covering the contact hole. Then the patterned oxide film
5
is used as a mask in selectively removing the amorphous silicon layer
4
. An amorphous silicon layer is deposited over the substrate
1
, and subjected to anisotropic etching to form sidewall amorphous silicon layers
6
at sides of the oxide film
5
. In this instance, the sidewall amorphous silicon layers
6
and the amorphous silicon layer
4
are connected electrically. As shown in
FIG. 1C
, all of the oxide film
5
is removed to form a cylindrical capacitor lower electrode
7
. As shown in
FIG. 1D
, silicon seeds are formed on a surface of the lower electrode using a seeding gas (Si
2
H
6
or SiH
4
) at approx. 570~620° C. in HSG-Si forming equipment, and the silicon seeds are annealed to form HSG-Si
8
with a rugged surface. Thus, a cylindrical lower electrode with HSG-Si and a mushroom shape can be formed. Though not shown, by forming a dielectric film and an upper electrode in succession on the lower electrode, a capacitor is completed.
A related art method for fabricating a box type capacitor will now be explained.
FIGS. 2A-2D
illustrate sections showing the steps of a method for fabricating a box type capacitor.
Referring to
FIG. 2A
, an interlayer insulating film
3
is deposited on a semiconductor substrate
1
having an impurity region
2
formed therein, and a portion of the interlayer insulating film
3
over the impurity region
2
is selectively removed to form a contact hole for a capacitor storage electrode. Then, an amorphous silicon layer
4
is deposited over the substrate
1
. The amorphous silicon layer
4
is formed of amorphous silicon doped with phosphorus at a concentration of approx. 2.0E20 atoms/cm
3
. As shown in
FIG. 2B
, an oxide film
5
is deposited over the substrate
1
. And, as shown in
FIG. 2C
, the oxide film
5
and the amorphous silicon layer
4
are subjected to photo-etching to remove portions of the oxide film
5
and the amorphous silicon layer
4
and leave the oxide film
5
and the amorphous silicon layer
4
in a region covering the contact hole. The oxide film
5
is then removed entirely, thereby completing a box type capacitor lower electrode
7
. As shown in
FIG. 2D
, silicon seeds are formed on a surface of the lower electrode using a seeding gas (Si
2
H
6
or SiH
4
) at approx. 570~620° C. in HSG-Si forming equipment, and the silicon seeds are annealed to form HSG-Si
8
with a rugged surface. Thus, a box type lower electrode with HSG-Si and a mashroom shape can be formed. Though not shown, by forming a dielectric film and an upper electrode in succession on the lower electrode, a capacitor is completed.
However, the related art structure of a capacitor and method for fabricating a capacitor in a DRAM as explained have the following problems.
The gap between storage nodes of capacitors in the semiconductor memory, due high density device packing, is less than 0.2 &mgr;m. The HSG-Si formed on the three dimensional structure like the cylindrical structure, are liable to fall off from regions having low adhesive forces, and are subsequently seized between the storage nodes without being removed even in a subsequent cleaning process. The dislodged HSG-Si form bridges which electrically short adjacent nodes. The dislodged HSG-Si typically has fallen off from peak points (end points in the cylindrical form) in the lower electrode. That is, the weak connection of the HSG-Si coming from lack of the amorphous silicon required for formation of the HSG-Si due to a relatively thin amorphous silicon, results in the falling off or hanging down of the HSG-Si during cleaning or high temperature processes, and causes a bridge between adjacent nodes.
Second, the HSG-Si in the case of box type capacitor are also liable to fall off from edges thereof to cause bridges between adjacent nodes.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a structure of a lower electrode of a capacitor and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a structure of a lower electrode of a capacitor and a method for fabricating the same, in which formation of HSG-Si at peak points of a cylindrical type lower electrode and edges of a box type lower electrode are prevented to inhibit the formation of
These and other objectives are achieved by providing a structure of a capacitor, comprising: a lower electrode having sides; and HSG-Si formed at sides of the lower electrode except upper portions of the sides.
These and other objectives a further achieved by providing a method for fabricating a capacitor, comprising: forming a lower electrode of a capacitor over a substrate, the lower electrode having lateral surfaces; adding impurity ions to upper portions of the lateral surfaces; and forming HSG-Si on surfaces of the lower electrode except the upper portions of the lateral surfaces.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5981334 (1999-11-01), Chien et al.
patent: 6077573 (2000-06-01), Kim et al.
patent: 6103587 (2000-08-01), Nakabeppu
patent: 6165830 (2000-12-01), Lin et al.
Cheon Young Il
Cho Bok Won
Choi Byung Jae
Birch & Stewart Kolasch & Birch, LLP
Hynix / Semiconductor Inc.
Perkins Pamela
Zarabian Amir
LandOfFree
Capacitor structure and method for fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Capacitor structure and method for fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Capacitor structure and method for fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3042455