Capacitor memory cell

Communications: electrical – Digital comparator systems

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Details

307238, 307246, G11C 1124, G11C 1134

Patent

active

040217884

ABSTRACT:
A dynamic capacitive memory cell having a storage node formed at the common junction of a fixed access capacitor and two MOS voltage variable capacitors. Data represented in the form of stored charge is written into the storage node through the fixed access capacitor under control of one of the MOS voltage variable capacitors and read out of the memory cell by a sensing device connected between the other voltage variable capacitor and ground. In another memory cell, one of the MOS voltage variable capacitors is replaced by an MOS transistor for preventing excess charge accumulation at the storage node.

REFERENCES:
patent: 3691537 (1972-09-01), Burgess et al.
patent: 3699544 (1972-10-01), Joynson et al.
patent: 3781831 (1973-12-01), Neugebauer et al.
patent: 3922650 (1975-11-01), Schaffer

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