Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-08-13
2004-08-10
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S528000, C257S532000, C438S329000, C438S957000
Reexamination Certificate
active
06774459
ABSTRACT:
FIELD OF INVENTION
The present invention relates to a CMOS active pixel sensor system. More specifically, the present invention is directed to a capacitor architecture useful for minimizing fixed pattern noise in a sample-and-hold stage of a CMOS active pixel sensor system.
BACKGROUND OF THE INVENTION
FIG. 1
is an illustration of a front-end portion of a color CMOS active pixel sensor (APS) imaging system
100
. The system
100
includes a N×M pixel array
110
comprised of pixels R, G, B which are sensitive to red, green, and blue colored light, respectively. The pixels R, G, B are typically arranged in a Bayer pattern, in which alternating rows are comprised of green/red and green/blue pixels in adjacent columns.
Any image focused upon the pixel array
110
causes the pixels R, G, B to convert the incident light into electrical energy. As will be described in greater detail below, this conversion typically results in a pixel outputting two electrical signals, namely the reset signal and a photo signal. Typically, CMOS APS imaging systems
100
operate by selecting and coupling a row of pixels, via signal lines
206
to a sample-and-hold circuit
120
. The sample-and-hold circuit
120
includes M subcircuits
121
which are coupled to a bus
122
. Each of the subcircuits
121
samples and holds the reset and photo signals from one of the pixels of the selected row. The M subcircuits
121
are sequentially selected to couple (via bus
122
, comprising reset signal line
122
r
and photo signal line
122
p
) the sampled reset and photo signals to a driver
130
. The driver
130
performs additional processing, which may include, for example, signal amplification or conditioning. The output of the driver
130
is then provided to an analog-to-digital converter
140
, which converts the sampled signals into a digital signal. The digital signal can then be provided to the remainder (not illustrated) of the APS imaging system
100
for further processing, manipulation, and storage. The above process is then repeated with the next pixel in the selected row by selecting the next sequential subcircuit
121
until the entire selected row has been processed. The above described processing is then performed on another row until every row in the array
110
has been processed. In alternative implementations the rest and photo signals are combined (e.g., subtracted) at the output of the sample-and-hold circuit
121
or in driver
130
so that the analog-to-digital converter receives a combined signal from each pixel.
FIG. 2
is a more detailed illustration of a pixel (R, G, or B). The pixel includes an element, such as photodiode
201
, for converting optical energy to electrical energy. The photodiode
201
is sensitive to green light if the pixel is a green (G) pixel, red light if the pixel is a red (R) pixel, or blue fight if the pixel is a blue (B) pixel. The pixels are made color sensitive by red, green, or blue filters as well known in the art. The output of the photodiode
201
is coupled to the gate of source-follower transistor
203
via the source/drain terminals of a transfer transistor
202
and node-A. A power source having a potential level of Vdd is coupled to column output line
206
via the source/drain terminals of the source follower transistor
203
and a row select transistor
204
, which has its gate coupled via signal line
210
to a ROW signal. The ROW signal is also coupled to other pixels (R, G, or B) in the same row. A power source having a reset voltage potential level of Vrst is coupled to the gate of the source-follower transistor
203
via the source/drain terminals of transistor
205
and node-A. The gate of transistor
205
is coupled to reset signal line
208
to the RST signal. The gate of the transfer transistor
202
is coupled via signal lines
209
and
207
to a transfer (TX) signal.
The pixel (R, G, or B) is operated in a manner to include a two phase process, wherein a reset signal is output during a first phase and a photo signal is output during a second phase. At the beginning of the first phase, the ROW signal of the pixel is asserted, thereby switching on transistor
204
. The TX signal is not asserted, thus transistor
202
is switched off, and the signal from the photodiode
201
is isolated from the gate of the source follower transistor
203
. The RST signal is asserted, thereby switching on transistor
205
and coupling the Vrst power source to the gate of the source follower transistor
203
via node-A. This causes a current to flow from the Vdd power source to the output line
206
. After a predetermined amount of time, the RST signal is then de-asserted, thereby switching off the source follower transistor
203
and terminating the first phase.
The second phase begins with the assertion of the TX signal, which switches on the transfer transistor
202
, thereby permitting the signal produced by the photodiode
201
to be applied to the gate of the source-follower transistor
203
. This causes a current to flow from the Vdd power source to the output line
206
. After a predetermined amount of time, the TX signal is dc-asserted, thereby switching off the transfer transistor
202
and terminating the second phase. The ROW signal is then de-asserted, thereby isolating the pixel from the output line
206
.
FIG. 3
is an illustration of the sample-and-hold subcircuit
121
. The subcircuit
121
includes a portion for sampling and holding the reset signal
301
r
and a portion for sampling and holding the photo signal
301
p
. Each of these sections
301
r
,
301
p
are coupled in parallel to signal line
301
, which is also coupled to the column output line
206
for a column of pixels (
FIG. 2
) at node-B. Each section
301
r
,
301
p
includes an isolation switch
351
,
352
coupled in series to a sampling capacitor
302
,
303
, respectively. Each sampling capacitor
302
,
303
is also coupled in series to its own column select switch
355
. Additionally, the sample-and-hold subcircuit
121
includes a crowbar switch
353
which may be used to couple the front plates of the sampling capacitors
302
,
303
. Each portion
301
r
,
301
p
further includes a clamping switch
354
, located between the sampling capacitor
302
,
303
and the column select switch
355
, which may be used to couple the back plates of the sampling capacitors
354
to a clamp voltage Vcl. The sample-and-hold subcircuit also includes a switchable current source
356
for the source follower transistor
203
(
FIG. 2
) of the pixel. The output of the sample-and-hold subcircuit
121
includes a photo signal at node-C and a reset signal at node-D. Nodes-C/D are coupled to respective lines
122
p
,
122
r
of a bus
122
(FIG.
1
).
The sample-and-hold subcircuit
121
operates as follows. The sample-and-hold subcircuit
121
is initialized by switching on the current source
356
(for line
301
), thereby coupling the output line
206
(
FIG. 2
) of the pixel (R, G, or B) to ground via line
301
. Switches
351
,
352
, and
353
are open. Both switches
354
are closed, and a clamping voltage Vcl is applied to the back plates of capacitors
302
,
303
. The clamping voltage Vcl is a stable voltage source over time (i.e., it has a very high rejection of variation of supply voltage), and is used to shift the output of the subcircuit
121
(at nodes-C/D) in order to match the output of the subcircuit
121
with the input of subsequent circuitry (e.g., driver
130
). Both switches
354
are then opened.
During the first phase of the pixel operation (in pixel R, G, or B of FIG.
2
), column select switches
355
are opened. Switch
352
is closed, to couple the reset portion
301
r
to the pixel output, which charges sampling capacitor
303
. Switch
352
is opened when the first phase of pixel output is completed. As the second phase of pixel output begins, switch
351
is closed to permit the second phase pixel output to charge sampling capacitor
302
. Switch
351
is opened when the second phase of pixel output is completed. These operations are performed by
Dickstein , Shapiro, Morin & Oshinsky, LLP
Flynn Nathan J.
Micro)n Technology, Inc.
Wilson Scott R
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