Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2007-04-17
2007-04-17
Menz, Doug (Department: 2891)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S068000, C257S071000, C257S300000
Reexamination Certificate
active
10609089
ABSTRACT:
The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or other integrated circuit device. The capacitive memory elements may have a generally oblong shape and may be capacitive elements. The capacitive memory elements may be disposed in a slanted orientation. The capacitive memory elements may be disposed in a non-orthogonal orientation. The capacitive memory elements may be disposed so that an axis through one of the plurality of capacitive memory elements is not generally parallel with an edge of the substrate. The axis may not be generally perpendicular with an orthogonal edge of the substrate. The plurality of capacitive memory elements may be arranged in a first row and a second row so that an axis through one of the plurality of capacitive memory elements located in the first row does not form an axis of any capacitive memory element in the second row.
REFERENCES:
patent: 6020235 (2000-02-01), Chang
patent: 6055655 (2000-04-01), Momohara
patent: 6120952 (2000-09-01), Pierrat et al.
patent: 6284419 (2001-09-01), Pierrat et al.
patent: 6319644 (2001-11-01), Pierrat et al.
patent: 6374396 (2002-04-01), Baggenstoss et al.
patent: 6401236 (2002-06-01), Baggenstoss et al.
patent: 6418008 (2002-07-01), Jost et al.
patent: 6440612 (2002-08-01), Baggenstoss
patent: 6569574 (2003-05-01), Baggenstoss
Murguia, James E., et al., Merging Focused Ion Beam Patterning and Optical Lithography in Device and Circuit Fabrication, Journal of Vacuum Science Technology B, Issue 8 (6), Nov./Dec. 1990, pp. 1374-1379.
Preuninger, J., et al., High Order Lens Aberration Monitor, Microelectronic Engineering 53 (2000), pp. 129-132.
Fletcher Yoder
Menz Doug
Micro)n Technology, Inc.
LandOfFree
Capacitor layout orientation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Capacitor layout orientation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Capacitor layout orientation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3734823